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Patent # Description
US-9,853,040 Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a semiconductor substrate; a plurality of first insulating layers and first conductive layers...
US-9,853,038 Three-dimensional memory device having integrated support and contact structures and method of making thereof
Memory openings and support openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. The support...
US-9,853,037 Integrated assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with...
US-9,853,036 Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
A nonvolatile memory ("NVM") bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and...
US-9,853,035 Layout scheme and method for forming device cells in semiconductor devices
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using...
US-9,853,034 Embedded memory with enhanced channel stop implants
An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer....
US-9,853,033 Memory device and manufacturing method thereof
A memory device includes an array of memory cells. At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around...
US-9,853,032 Semiconductor devices and methods for fabricating the same
A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A...
US-9,853,031 Semiconductor device
A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a...
US-9,853,030 Fin field effect transistor
Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A...
US-9,853,029 Integrated circuit device and method of manufacturing the same
An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The...
US-9,853,028 Vertical FET with reduced parasitic capacitance
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a...
US-9,853,027 Methods of forming patterns, and apparatuses comprising FinFETs
Some embodiments include a method of forming a pattern. A semiconductor substrate has first and second rows extending along a first direction, and which...
US-9,853,026 FinFET device and fabrication method thereof
A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The...
US-9,853,025 Thin film metallic resistors formed by surface treatment of insulating layer
A semiconductor device having an integrated thin film metallic resistor device which is formed by a process which includes depositing a conformal layer of...
US-9,853,024 Semiconductor device
A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a...
US-9,853,023 Semiconductor device and semiconductor package
A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common...
US-9,853,022 MIM capacitor formation in RMG module
A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a...
US-9,853,021 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation...
US-9,853,020 Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit
Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver...
US-9,853,019 Integrated circuit device body bias circuits and methods
A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein,...
US-9,853,018 Optoelectronic semiconductor chip and optoelectronic component
An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence includes a first semiconductor region of a first...
US-9,853,017 Light emitting device package and light emitting device package module
Disclosed herein is a light emitting device package and a light emitting device package module. The light emitting device package includes: a base including a...
US-9,853,016 Systems and methods for high-speed, low-profile memory packages and pinout designs
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit ("IC") package substrate capable of...
US-9,853,015 Semiconductor device with stacking chips
A semiconductor device includes a first chip, a spacer, and a second chip. The first chip and the spacer are disposed on a substrate. The second chip has a...
US-9,853,014 Electronic component, electronic apparatus, and method of manufacturing electronic apparatus
An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second...
US-9,853,013 Semiconductor device having stacked chips
According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for...
US-9,853,012 Semiconductor packages having through electrodes and methods of fabricating the same
Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level...
US-9,853,011 Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a conductive structure, a semiconductor element disposed on and electrically connected to the conductive structure, a...
US-9,853,010 Method of fabricating a semiconductor package
Provided is a method of fabricating a semiconductor package. The method includes providing a package substrate including a pad, mounting a semiconductor chip...
US-9,853,009 Semiconductor module having a conductor member for reducing thermal stress
In the semiconductor module according to the present invention, a conducting member which is used to electrically connect a semiconductor element arranged on a...
US-9,853,008 Connecting techniques for stacked CMOS devices
In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is...
US-9,853,007 Method for producing an integrated circuit package and apparatus produced thereby
A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes...
US-9,853,006 Semiconductor device contact structure having stacked nickel, copper, and tin layers
A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by...
US-9,853,005 Semiconductor device and method of manufacturing the same
An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the...
US-9,853,004 Interconnections for a substrate associated with a backside reveal
An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An...
US-9,853,003 Fan-out semiconductor package
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first...
US-9,853,002 Semiconductor device
A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a...
US-9,853,001 Prevention of reverse engineering of security chips
A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric...
US-9,853,000 Warpage reduction in structures with electrical circuitry
To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing...
US-9,852,999 Wafer reinforcement to reduce wafer curvature
A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor...
US-9,852,998 Ring structures in device die
A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically...
US-9,852,997 Hybrid wafer dicing approach using a rotating beam laser scribing process and plasma etch process
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,852,996 Substrate and method for labeling signal lines thereof
A substrate is disclosed. The substrate includes a transparent underlayer, a plurality of signal lines on the transparent underlayer, and a plurality of labels...
US-9,852,995 Semiconductor device
A semiconductor device includes a first semiconductor chip having a first surface with a semiconductor element and a second surface opposing the first surface....
US-9,852,994 Embedded vialess bridges
Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are...
US-9,852,993 Lateral high voltage integrated devices having trench insulation field plates and metal field plates
A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region...
US-9,852,992 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric...
US-9,852,991 Semiconductor structure and fabrication method thereof
A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric...
US-9,852,990 Cobalt first layer advanced metallization for interconnects
A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features...
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