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Patent # Description
US-9,852,989 Power grid of integrated circuit
Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power...
US-9,852,988 Increased contact alignment tolerance for direct bonding
A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and...
US-9,852,987 Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a substrate. The device further includes a first interconnect which includes a first layer provided on the...
US-9,852,986 Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is...
US-9,852,985 Conductive terminal on integrated circuit
A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The...
US-9,852,984 Cut first alternative for 2D self-aligned via
A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided....
US-9,852,983 Fabricating method of anti-fuse structure
A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the...
US-9,852,982 Anti-fuses with reduced programming voltages
Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin....
US-9,852,981 III-V compatible anti-fuses
An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region...
US-9,852,980 Interconnect structure having substractive etch feature and damascene feature
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive...
US-9,852,979 Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips
An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor...
US-9,852,978 Metal layout for radio-frequency switches
Metal layout for radio-frequency (RF) switches. In some embodiments, an RF switching device can include a plurality of field-effect transistors (FETs) arranged...
US-9,852,977 Package substrate
This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed...
US-9,852,976 Semiconductor package and fabricating method thereof
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various...
US-9,852,975 Wiring board, electronic device, and electronic module
A wiring board according to the present invention includes: an insulating base including a main face, a side face, and a notch portion opened in the main face...
US-9,852,973 Manufacturing method of chip package and package substrate
A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on...
US-9,852,972 Semiconductor device and method of aligning semiconductor wafers for bonding
A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one...
US-9,852,971 Interposer, semiconductor package structure, and semiconductor process
An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and...
US-9,852,970 Wiring substrate
A wiring substrate includes a first wiring layer, a first insulation layer, and a second wiring layer. The first insulation layer covers an upper surface and a...
US-9,852,969 Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of...
US-9,852,968 Semiconductor device including a sealing region
The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a...
US-9,852,967 Lead frame structure for light emitting diode
A lead frame structure of a light emitting diode includes a ceramic bed, a metal layer and a plastic seat. The metal layer has a first metal circuit area, a...
US-9,852,966 Semiconductor package
A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral...
US-9,852,965 Semiconductor devices with through electrodes and methods of fabricating the same
Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor...
US-9,852,964 Through-body via formation techniques
Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed...
US-9,852,963 Microprocessor assembly adapted for fluid cooling
A microprocessor assembly adapted for fluid cooling can include a semiconductor die mounted on a substrate. The semiconductor die can include an integrated...
US-9,852,962 Waterproof electronic device and manufacturing method thereof
A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating...
US-9,852,961 Packaged semiconductor device having an encapsulated semiconductor chip
A packaged semiconductor device includes a semiconductor component, first and second heat dissipation means disposed between the semiconductor component and the...
US-9,852,960 Underfill dispensing using funnels
Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill...
US-9,852,959 Corrosion resistant chip sidewall connection with crackstop and hermetic seal
The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures...
US-9,852,958 Container for housing electronic component and electronic device
A container for housing an electronic component includes: a container body including a bottom plate and a polygonal side wall surrounding a central region of...
US-9,852,957 Testing, manufacturing, and packaging methods for semiconductor devices
Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes...
US-9,852,956 Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices
Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented...
US-9,852,955 Method and arrangement for analyzing a semiconductor element and method for manufacturing a semiconductor component
According to the improved concept, a method for analyzing a semiconductor element comprising polymer residues located on a surface of the semiconductor element...
US-9,852,954 Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor...
US-9,852,953 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-9,852,952 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV)...
US-9,852,951 Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
US-9,852,950 Superimposed transistors with auto-aligned active zone of the upper transistor
Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug...
US-9,852,949 Wafer processing method
A wafer is divided into device chips each of which is surrounded by a mold resin. The wafer has a plurality of devices arranged like a matrix with a spacing...
US-9,852,948 Apparatus and method for processing a substrate
A method of processing a substrate is disclosed. The method includes the following steps: providing a substrate body having a surface; placing a die on the...
US-9,852,947 Forming sidewall spacers using isotropic etch
A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed,...
US-9,852,946 Self aligned conductive lines
A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to...
US-9,852,945 Method of manufacturing a semiconductor device having a cell field portion and a contact area
A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method...
US-9,852,944 Backside contact to a final substrate
Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a...
US-9,852,943 Method for manufacturing a conductor to be used as interconnect member
A method for manufacturing a conductor may include the following steps: preparing a substrate structure and a first metal set, wherein the substrate structure...
US-9,852,942 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a plurality of columnar parts. The stacked body is provided...
US-9,852,941 Stacked conductor structure and methods for manufacture of same
A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may...
US-9,852,940 Method for forming a reliable solderable contact
A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after...
US-9,852,939 Solderable contact and passivation for semiconductor dies
A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after...
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