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Patent # Description
US-9,852,835 Oxide interface displaying electronically controllable ferromagnetism
A structure includes an electronically controllable ferromagnetic oxide structure that includes at least three layers. The first layer comprises STO. The second...
US-9,852,834 Adjustable center pole
An adjustable solenoid assembly with an adjustable threaded pole having an interference fit section to be used with a complementary threaded receiver (e.g., the...
US-9,852,833 Magnetization alignment in a thin-film device
We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation....
US-9,852,832 Magnetic field sensor and associated method that can sense a position of a magnet
A magnetic field sensor, a magnetic assembly, and a method provide circuits and techniques for or measuring one or more displacement angles of a magnet using...
US-9,852,831 Superconducting magnet
This superconducting magnet includes: a superconducting coil that is formed by winding a first superconducting wire rod; a second superconducting wire rod,...
US-9,852,830 Apparatus and methods for generating a precise resistor
In one embodiment, an apparatus comprising a first resistor, the first resistor comprising a first type of resistor having a plurality of metal wires in...
US-9,852,829 Metal nitride material for thermistor, method for producing same, and film thermistor sensor
Provided are a metal nitride material for a thermistor, which exhibits high reliability and high heat resistance and can be directly deposited on a film or the...
US-9,852,828 Edge insulation structure for electrical cable
A cable (2100) includes one or more conductor sets, one or more dielectric unitary blocks (2102) or reservoirs, first and second conductive shielding films...
US-9,852,827 Data cable and motor vehicle with the data cable
A novel data cable achieves good transmission quality in automotive Internet applications. The data cable has a transmission core with only a single stranded...
US-9,852,826 Cable with semiconductive layer made of polypropylene composition and improved long term thermal stability
Described herein is a cable that includes a conductor surrounded by at least one semiconductive layer, wherein the layer comprises a polymer composition...
US-9,852,825 Conductive composition and solid electrolytic capacitor obtained using aforementioned composition
Provided are: a conductive composition containing a conductive polymer (A) satisfying the below-mentioned condition (i), and a compound (B) having at least 3...
US-9,852,824 Methods for controlling pore morphology in aerogels using electric fields and products thereof
In one embodiment, an aerogel or xerogel includes column structures of a material having minor pores therein and major pores devoid of the material positioned...
US-9,852,823 Methods and systems for producing fissile material from fertile feedstock
A method for generating a fissile material is described. The method includes positioning a fertile, non-fissile material within outer space, the position within...
US-9,852,822 High-density subterranean storage system for nuclear fuel and radioactive waste
An underground ventilated system for storing nuclear waste materials. The system includes a storage module having an outer shell defining an internal cavity and...
US-9,852,821 Nuclear fuel assembly handling apparatus
A fuel assembly handling tool that can be lowered onto the top nozzle of a fuel assembly, positively latch the top nozzle, unlatch from the top nozzle, and be...
US-9,852,820 Nuclear steam supply system
A nuclear steam supply system utilizing gravity-driven natural circulation for primary coolant flow through a fluidly interconnected reactor vessel and a steam...
US-9,852,819 Passive nuclear reactor cooling system using compressed gas energy and coolant storage outside nuclear plant
A passive safety system for a nuclear power plant (100) cools a nuclear power plant after shutdown (SCRAM) even when all primary water circulation has been...
US-9,852,818 Systems and methods for controlling reactivity in a nuclear fission reactor
Illustrative embodiments provide a reactivity control assembly for a nuclear fission reactor, a reactivity control system for a nuclear fission reactor having a...
US-9,852,817 Control rod drive mechanism built in nuclear reactor
Disclosed is a control rod drive mechanism. More specifically, the control rod drive mechanism includes a guide member 100 disposed in a nuclear reactor to...
US-9,852,816 Efficient compact fusion reactor
An efficient compact nuclear fusion reactor for use as a neutron source or energy source is described. The reactor comprises a toroidal plasma chamber and a...
US-9,852,815 Semiconductor memory device and memory system including the same
A semiconductor memory device includes a normal memory block including a plurality of normal memory cells, a redundant memory block including a plurality of...
US-9,852,814 Rupture control device and semiconductor device to improve yield
A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a...
US-9,852,813 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-9,852,812 Storage apparatus, memory controller, control method for storage apparatus, and program
There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to...
US-9,852,811 Device and method for detecting controller signal errors in flash memory
In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory...
US-9,852,810 Optimizing fuseROM usage for memory repair
A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each...
US-9,852,809 Test mode circuit for memory apparatus
Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including...
US-9,852,808 Memory testing circuit and testing method using same
A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test...
US-9,852,807 Content addressable memory in an emulation system
Disclosed herein are components of an emulation system capable of efficiently recreating the functionality a CAM/TCAM memory circuit. Rather than using...
US-9,852,806 System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding
Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions...
US-9,852,805 Write enhancement for one time programmable (OTP) semiconductors
A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass...
US-9,852,804 Nonvolatile memory device, memory system, method of operating nonvolatile memory device, and method of...
A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is...
US-9,852,803 Dummy word line control scheme for non-volatile memory
A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or...
US-9,852,802 Memory system with multiple programming modes
A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a first program mode and a second program mode....
US-9,852,801 Method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell
A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate...
US-9,852,800 Adaptive determination of program parameter using program of erase rate
Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one...
US-9,852,799 Configuration parameter management for non-volatile data storage
Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage...
US-9,852,798 Buffered automated flash controller connected directly to processor memory bus
A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory...
US-9,852,797 Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second...
US-9,852,796 Nonvolatile memory devices and methods of operating the same
A nonvolatile memory device includes memory blocks that each include cell strings formed vertically on a substrate. The cell strings are coupled to a plurality...
US-9,852,795 Methods of operating nonvolatile memory devices, and memory systems including nonvolatile memory devices
A method of operating a nonvolatile memory device includes performing a first memory operation on a first memory block of a plurality of memory blocks and a...
US-9,852,794 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,852,793 Methods for programming and accessing DDR compatible resistive change element arrays
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and...
US-9,852,792 Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory...
US-9,852,791 Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof
A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the...
US-9,852,790 Circuit methodology for highly linear and symmetric resistive processing unit
A resistive processing unit (RPU) includes a circuit including at least two current mirrors connected in series, and a capacitor connected with the at least two...
US-9,852,789 Transient current-protected threshold switching devices systems and methods
Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and...
US-9,852,788 Multipage program scheme for flash memory
A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed...
US-9,852,787 Semiconductor device, electronic component, and electronic device
Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the...
US-9,852,786 Semiconductor memory device that varies voltage levels depending on which of different memory regions thereof...
A semiconductor memory device includes a semiconductor memory chip including a plurality of regions of memory cells, including a first memory region and a...
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