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Patent # Description
US-9,852,074 Cache-optimized hash table data structure
Various exemplary embodiments relate to a system for hashing a value into a cache, the system including a processor for performing a series of instructions; a...
US-9,852,073 System and method for data redundancy within a cache
In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the...
US-9,852,072 Methods for host-side caching and application consistent writeback restore and devices thereof
A method, non-transitory computer readable medium, and device that assists with file-based host-side caching and application consistent write back includes...
US-9,852,071 Granting exclusive cache access using locality cache coherency state
A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a...
US-9,852,070 Cache memory system using a tag comparator to determine update candidates and operating method thereof
A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address...
US-9,852,069 RAM disk using non-volatile random access memory
A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS)...
US-9,852,068 Method and apparatus for flash memory storage mapping table maintenance via DRAM transfer
The method for maintaining a storage mapping table is introduced. After a total number of logical blocks, which exceeds a specified number, have been programmed...
US-9,852,067 Data storage device and operating method thereof
A data storage device includes a nonvolatile memory device including a plurality of memory units; and a controller suitable for acquiring a temperature...
US-9,852,066 Systems and methods of address-aware garbage collection
A method includes determining a first logical block address (LBA) range of a first set of data units of a first candidate block of the memory. The method also...
US-9,852,065 Method and apparatus for reducing data program completion overhead in NAND flash
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing...
US-9,852,064 Method, apparatus and computer program for management of flash memory
A system on chip includes a memory information read unit and a memory feature setting unit. The memory information read unit is configured to read standard...
US-9,852,063 Memory device and non-transitory computer readable recording medium
According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile...
US-9,852,062 Memory controller and accessing system utilizing the same
A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is...
US-9,852,061 Memory device and operating method of memory device
A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata...
US-9,852,060 Storage class memory (SCM) memory mode cache system
An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory...
US-9,852,059 NVS thresholding for efficient data management
For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by...
US-9,852,058 NVS thresholding for efficient data management
For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by...
US-9,852,057 Light-weight on-chip signal monitor with integrated memory management and data collection
Embodiments of a device and method to automatically acquire signal quality metrics in a digital communication system are disclosed. The device may include...
US-9,852,056 Multi-level memory compression
According to one embodiment of the present disclosure, an approach is provided in which a processor selects a page of data that is compressed by a first...
US-9,852,055 Multi-level memory compression
According to one embodiment of the present disclosure, an approach is provided in which a processor selects a page of data that is compressed by a first...
US-9,852,054 Elastic caching for Java virtual machines
A mechanism is provided for managing memory of a runtime environment executing on a virtual machine. The mechanism includes an elastic cache made of objects...
US-9,852,053 Dynamic software inspection tool
A dynamic software inspection tool is disclosed. The tool executes a method which may include obtaining a status for at least one graphical object from the...
US-9,852,052 Trusted execution of called function
A copy is made of at least a part a stack. A caller return address of a calling function in the stack is verified as trusted. A caller return address of a...
US-9,852,051 Second failure data capture in co-operating multi-image systems
A computer system and computer program captures diagnostic trace information in a computer system having a plurality of software images. Information is received...
US-9,852,050 Selecting computing resources
Systems and methods are described for distributing pool resources. One method includes maintaining a plurality of groups of computing resources, wherein each...
US-9,852,049 Screenshot validation testing
Embodiments of the present invention disclose a method, computer program product, and system for comparing screenshots of an application interface. In one...
US-9,852,048 Simulating process variable changes during process runtime
Embodiments of the present invention provide methods and systems for simulating variable changes during runtime of a process. The method includes recording...
US-9,852,047 Recording program execution
Among other things, a method includes, at a computer system on which one or more computer programs are executing, receiving a specification defining types of...
US-9,852,046 Method and system for automated debugging memory allocation and memory release
A method and system for debugging memory allocation and memory release may include recording execution events of an execution run of a program including data...
US-9,852,045 Debugging program code
Embodiments for debugging program code are provided. In response to a debug comparison request, (i) a first set of debugging operations are initiated on a first...
US-9,852,043 Using principles of natural selection to optimize a cloud-computing genome
A method and associated systems for optimizing a computing platform. A processor joins sets of configurable parameters into groups that each identifies a...
US-9,852,042 Dynamically choosing data to collect in a system
Method to perform an operation comprising collecting, metric data for a first job upon determining that the first job: uses a first resource of a computing...
US-9,852,041 Systems and methods for categorizing exceptions and logs
Techniques for categorizing exceptions and logs are described. For example, exception data of an exception that occurred on a machine is accessed. The exception...
US-9,852,040 Methods for updating memory maps of a system-on-chip
This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the...
US-9,852,039 Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices
An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a...
US-9,852,038 Debugging system and debugging method of multi-core processor
The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target...
US-9,852,037 Efficiency of cycle-reproducible debug processes in a multi-core environment
An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or...
US-9,852,036 Configurable input/output sub-channels for optimized diagnostics
A novel diagnostics and verifiable input/output (DVIO) channel may reduce fixed diagnostic circuitry and allow standard input/output channels to be repurposed...
US-9,852,035 High availability dynamic restart priority calculator
Restarting virtual machines is provided. Each server in a plurality of servers is monitored within a client virtual machine host environment via a network. In...
US-9,852,034 Efficient high availability for a SCSI target over a fibre channel
For efficient high availability for a multi-node cluster using a processor device in a computing environment, using duplicate, standby host-bus adaptors (HBAs)...
US-9,852,033 Method of recovering application data from a memory of a failed node
A method of recovering application data from the memory of a failed node in a computer system comprising a plurality of nodes connected by an interconnect and...
US-9,852,032 Data storage devices and data maintenance methods
A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block...
US-9,852,031 Computer system and method of identifying a failure
A computer system for realizing increased speed of identifying extent of a failure in a messaging system, provided with: a first computer including a message...
US-9,852,029 Managing a computing system crash
A method, system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two...
US-9,852,028 Managing a computing system crash
A system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two classifications,...
US-9,852,027 Virtual machine high availability management
Systems and methods for virtual machine high availability management. An example method may comprise: identifying a virtual machine; receiving information...
US-9,852,026 Efficient application recovery in an information management system based on a pseudo-storage-device driver
The disclosed systems and methods enable an application to start operating and servicing users soon after and during the course of its backup data being...
US-9,852,025 Protecting data stored on a solid state drive
Disclosed are different types of mechanisms for protecting data stored on a solid state drive or device (SSD) without erasing that data and/or without...
US-9,852,024 Apparatus and method for read time control in ECC-enabled flash memory
In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of V.sub.CC values without wasted time by allocating a...
US-9,852,023 Memory system and information processing system
A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, the ECC circuit, and a processor. The...
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