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Patent # Description
US-9,871,147 Photodetector
A photodetector including a substrate, a light absorption layer arranged over the substrate, the light absorption layer including a stack including a...
US-9,871,146 Solar cell and method for manufacturing the same
A solar cell includes a substrate formed of n-type single crystal silicon, an emitter region of a p-type which is positioned at a first surface of the substrate...
US-9,871,145 Semiconductor device, manufacturing method thereof, and electronic device
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor...
US-9,871,144 Thin film transistor substrate
A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the...
US-9,871,143 Semiconductor device and manufacturing method thereof
A semiconductor device that is suitable for miniaturization. A method for manufacturing a semiconductor device includes the steps of forming a semiconductor,...
US-9,871,142 Display device and method of manufacturing display device
A method of manufacturing a display device is provided. The display device includes a display region divided into a first display region and a second display...
US-9,871,141 Thermally tuning strain in semiconductor devices
A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon...
US-9,871,139 Sacrificial epitaxial gate stressors
A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial...
US-9,871,138 Semiconductor device and method of fabricating semiconductor device
The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial...
US-9,871,137 Method for forming semiconductor device structure
The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation...
US-9,871,136 Semiconductor device
A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate...
US-9,871,135 Semiconductor device and method of making
A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type...
US-9,871,134 Power MOSFETs and methods for manufacturing the same
A semiconductor device and the method of manufacturing the same are provided. The semiconductor device includes a substrate, a source region, a drain region, a...
US-9,871,133 Lateral DMOS device with dummy gate
An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the...
US-9,871,132 Extended drain metal-oxide-semiconductor transistor
Devices and methods for forming a device are disclosed. A transistor is formed on the substrate. The transistor includes a gate, a source and a drain. An...
US-9,871,131 Semiconductor device with insulating section of varying thickness
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the...
US-9,871,130 Nitride semiconductor device and manufacturing method thereof
A nitride semiconductor device includes: a first nitride semiconductor layer serving as an electron transit layer; a second nitride semiconductor layer formed...
US-9,871,129 Thyristor, a method of triggering a thyristor, and thyristor circuits
A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region;...
US-9,871,128 Bipolar semiconductor device with sub-cathode enhancement regions
There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device...
US-9,871,127 Semiconductor device and method for manufacturing the same
A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in...
US-9,871,126 Discrete semiconductor transistor
A discrete semiconductor transistor includes a gate resistor electrically coupled between a gate electrode terminal and a gate electrode of the discrete...
US-9,871,125 Bipolar transistor
A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body...
US-9,871,124 Method of IGZO and ZnO TFT fabrication with PECVD SiO.sub.2 passivation
The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source...
US-9,871,123 Field effect transistor and manufacturing method thereof
A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge...
US-9,871,122 Methods of fabricating a semiconductor device
A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy...
US-9,871,121 Semiconductor device having a gap defined therein
In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the...
US-9,871,120 Fin field-effect transistor and fabrication method thereof
A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of...
US-9,871,119 Method of manufacturing a termination arrangement for a vertical MOSFET
Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure...
US-9,871,118 Semiconductor structure with an L-shaped bottom plate
A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure...
US-9,871,117 Vertical transistor devices for embedded memory and logic technologies
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region...
US-9,871,116 Replacement metal gate structures
Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method...
US-9,871,115 Doped poly-silicon for polyCMP planarity improvement
A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the...
US-9,871,114 Metal gate scheme for device and methods of forming
Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate,...
US-9,871,113 Semiconductor process
A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer,...
US-9,871,112 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer...
US-9,871,111 Semiconductor device and method
A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is...
US-9,871,110 Semiconductor device
It is aimed to reduce a current concentration at the edge of the contact electrode. Provided is a semiconductor device including a semiconductor layer, a first...
US-9,871,109 Semiconductor device
A semiconductor device according to the present invention includes, in a termination region, a p- type breakdown voltage holding region that is an impurity...
US-9,871,108 Nitride semiconductor device
A nitride semiconductor device according to the present invention includes a nitride semiconductor layer having a gate, a source and a drain and a field plate...
US-9,871,107 Device with a conductive feature formed over a cavity and method therefor
An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the...
US-9,871,106 Heterogeneous pocket for tunneling field effect transistors (TFETs)
Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity...
US-9,871,105 Method of forming an isolation structure in a well of a substrate
A method includes forming an isolation structure in a well of a substrate. A portion of the isolation structure protrudes from a top surface of the well. The...
US-9,871,104 Nanowire semiconductor device structure and method of manufacturing
A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the...
US-9,871,103 Semiconductor device
A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and...
US-9,871,102 Method of forming a single-crystal nanowire finFET
A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire...
US-9,871,101 Semiconductor device and manufacturing method thereof
A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate,...
US-9,871,100 Trench structure of semiconductor device having uneven nitrogen distribution liner
A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation...
US-9,871,099 Nanosheet isolation for bulk CMOS non-planar devices
A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation...
US-9,871,098 Semiconductor device with suppressed decrease in breakdown voltage of an insulation film and manufacturing...
A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor...
US-9,871,097 Thin film transistor, method for manufacturing thin film transistor, and organic EL display device
A thin film transistor includes: a gate electrode; a gate insulating layer above the gate electrode; an oxide semiconductor layer disposed above the gate...
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