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Patent # Description
US-9,871,046 SRAM circuits with aligned gate electrodes
A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region...
US-9,871,045 Semiconductor device with damascene bit line and method for manufacturing the same
A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second...
US-9,871,044 Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related...
Volatile memory cells including dielectric materials exhibiting a nonlinear capacitance as a function of voltage. The volatile memory cells comprise a source...
US-9,871,043 4F2 SCR memory device
A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F.sup.2. This array of threshold...
US-9,871,042 Semiconductor device having fin-type patterns
A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second...
US-9,871,041 Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
A method of forming a fin field effect transistor (finFET) with a doped substrate region, including forming a plurality of vertical fins on a substrate, forming...
US-9,871,040 Semiconductor device comprising a standard cell
Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard...
US-9,871,039 Resistance mitigation in physical design
Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a...
US-9,871,038 Semiconductor device including fin structures and manufacturing method thereof
A semiconductor device includes device areas where a Fin FET is disposed and a non-device area disposed between the device areas, which includes a dummy...
US-9,871,036 Semiconductor device
A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of...
US-9,871,035 Semiconductor device with metal silicide blocking region and method of manufacturing the same
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a gate stack on a semiconductor substrate. In some...
US-9,871,034 Semiconductor device and structure
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal...
US-9,871,033 Semiconductor integrated circuit device
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring...
US-9,871,032 Gate-grounded metal oxide semiconductor device
A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD)...
US-9,871,031 Semiconductor device and an electronic apparatus
A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a...
US-9,871,030 Plasma protection diode for a HEMT device
A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process....
US-9,871,029 Bus driver / line driver
A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing...
US-9,871,028 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill...
US-9,871,027 Semiconductor device having mesh-patterned wirings
A semiconductor device includes a mesh-patterned power source wiring that supplies respective circuits with a power source voltage supplied to a plurality of...
US-9,871,026 Embedded memory and power management subpackage
Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a...
US-9,871,025 Commutation cell
A commutation cell having at least one electrical capacitor, at least one controllable semiconductor switch and at least one semiconductor which is connected in...
US-9,871,024 Light-emitting apparatus and illumination apparatus
A light-emitting apparatus is provided. The light-emitting apparatus includes a first and second light-emitting elements disposed on a substrate. A sealing...
US-9,871,023 Method for transfer of semiconductor devices
A method of transferring semiconductor devices to a product substrate includes positioning a surface of the product substrate to face a first surface of a...
US-9,871,022 Light emitting lamp
Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying...
US-9,871,021 Data storage device having multi-stack chip package and operating method thereof
Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip...
US-9,871,020 Through silicon via sharing in a 3D integrated circuit
The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated...
US-9,871,019 Flipped die stack assemblies with leadframe interconnects
A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a...
US-9,871,018 Packaged semiconductor devices and methods of packaging semiconductor devices
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device...
US-9,871,017 Multi-level chip interconnect
Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated...
US-9,871,016 Semiconductor package
Provided is a semiconductor package including a substrate; at least one semiconductor chip mounted on the substrate; a molding element, which is arranged on the...
US-9,871,015 Wafer level package and fabrication method
A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip,...
US-9,871,014 3D-joining of microelectronic components with conductively self-adjusting anisotropic matrix
3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix...
US-9,871,013 Contact area design for solder bonding
A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first...
US-9,871,012 Method and apparatus for routing die signals using external interconnects
Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides...
US-9,871,011 Semiconductor package using a contact in a pleated sidewall encapsulant opening
A semiconductor package, and a method of manufacturing thereof, comprising a contact in a plated sidewall encapsulant opening, substantially as shown in and/or...
US-9,871,010 Tin alloy electroplating solution for solder bumps including perfluoroalkyl surfactant
Disclosed is a tin-based electroplating solution for forming solder bumps of a flip chip package. The tin-based electroplating solution includes tin...
US-9,871,009 Semiconductor device and method
A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element...
US-9,871,008 Monolithic microwave integrated circuits
Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high...
US-9,871,007 Packaged integrated circuit device with cantilever structure
Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device...
US-9,871,006 Semiconductor module having a solder-bonded cooling unit
A semiconductor module including an insulated circuit substrate having a substrate, a circuit layer on a front surface of the substrate, and a metal layer on a...
US-9,871,005 Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top...
US-9,871,004 Laminates of integrated electromagnetically shieldable thin inductors, capacitors, and semiconductor chips
Semiconductor chip laminates and inductive, capacitive, and electromagnetic shielding laminate structures that can be integrated together to form electronic...
US-9,871,003 Mark forming method and device manufacturing method
A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is...
US-9,871,001 Feeding overlay data of one layer to next layer for manufacturing integrated circuit
A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the...
US-9,871,000 Semiconductor device and manufacturing method, and electronic apparatus
The present disclosure relates to a semiconductor device and a manufacturing method, and an electronic apparatus that enable manufacturing of a stacked...
US-9,870,999 Device and method for alignment of vertically stacked wafers and die
A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern...
US-9,870,998 Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure
Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly...
US-9,870,997 Integrated fan-out package and method of fabricating the same
A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in...
US-9,870,996 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of...
US-9,870,995 Formation of copper layer structure with self anneal strain improvement
A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first...
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