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Patent # Description
US-9,870,994 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric...
US-9,870,993 Simultaneous formation of liner and metal conductor
An advanced metal conductor structure and a method for constructing the structure are described. A method for fabricating an advanced metal conductor structure...
US-9,870,992 Power line layout structure for semiconductor device
A power line layout structure of the semiconductor device may include first through fifth power lines. The first and second power lines may be located at a...
US-9,870,991 Semiconductor device
A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be...
US-9,870,990 Apparatuses including stair-step structures and methods of forming the same
Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material,...
US-9,870,989 Electrical fuse and/or resistor structures
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
US-9,870,988 Method of producing a semiconductor device with through-substrate via covered by a solder ball
A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied...
US-9,870,987 Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes an insulator. The device further includes a plug provided in the insulator, the plug including a first...
US-9,870,986 Single or multi chip module package and related methods
Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and...
US-9,870,985 Semiconductor package with clip alignment notch
An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the...
US-9,870,984 Power field-effect transistor (FET), pre-driver, controller, and sense resistor integration for multi-phase...
Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for...
US-9,870,983 Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing...
A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the...
US-9,870,982 Distributed on-chip decoupling apparatus and method using package interconnect
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having...
US-9,870,980 Semiconductor package with through silicon via interconnect
The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV...
US-9,870,979 Double-sided segmented line architecture in 3D integration
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided...
US-9,870,978 Heat spreading in molded semiconductor packages
A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and...
US-9,870,977 Semiconductor device with heat information mark
A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat...
US-9,870,976 Method of manufacture for a semiconductor device
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal...
US-9,870,975 Chip package with thermal dissipation structure and method for forming the same
Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that...
US-9,870,974 Power conversion apparatus including wedge inserts
A power conversion apparatus includes: a circuit body including a switching device; a base member forming a first concave portion and a cooling surface; and a...
US-9,870,973 Cooling device and device
Heat dissipaters 120a, 120b are thermally coupled to a memory 220 and a CPU 230 (heat generating components) disposed on a top surface (a first surface) of a...
US-9,870,972 Thermosetting resin molded article
A thermosetting resin molded article including: a metal member; a first thermosetting resin layer containing a chelating agent in an amount of 0.5% by mass or...
US-9,870,971 Epoxy resin composition for encapsulating a semiconductor device and semiconductor device prepared using the same
An epoxy resin composition and a semiconductor device, the composition including an epoxy resin; a curing agent; an inorganic filler; a curing catalyst; and a...
US-9,870,970 Cured product
The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an LED...
US-9,870,969 Substrate
The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper...
US-9,870,968 Repackaged integrated circuit and assembly method
A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which...
US-9,870,967 Plurality of seals for integrated device package
Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a...
US-9,870,966 Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of...
Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ("NCEM") of...
US-9,870,965 Semiconductor device
Provided is a semiconductor device including a semiconductor substrate; a dummy trench that is formed on a front surface side of the semiconductor substrate; an...
US-9,870,964 Method of manufacturing semiconductor device by determining and selecting cooling recipe based on temperature
The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving a processing uniformity of...
US-9,870,963 Endpoint booster systems and methods for optical endpoint detection
An endpoint booster transports an optical signal from inside of a plasma etch chamber through a viewport to an optical cable outside of the plasma etch chamber....
US-9,870,962 Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,870,961 Wafer processing method
Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a...
US-9,870,960 Capacitance monitoring using X-ray diffraction
A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak...
US-9,870,959 Method and apparatus for testing a flip-chip assembly during manufacture
Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC...
US-9,870,958 Forming CMOSFET structures with different contact liners
A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second...
US-9,870,957 Vertical fin field effect transistor (V-FinFET), semiconductor device having V-FinFET and method of fabricating...
A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an...
US-9,870,956 FinFETs with nitride liners and methods of forming the same
An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side...
US-9,870,955 Formation method of semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy...
US-9,870,954 Simultaneous formation of source/drain openings with different profiles
A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate,...
US-9,870,953 System on chip material co-integration
A method, and the resulting structure, of a semiconductor device where a first and second gate structure is formed above a Semiconductor-on-Insulator (SOI)...
US-9,870,952 Formation of VFET and finFET
An embodiment may include a method of forming a semiconductor device. The method may include forming a first fin in a VFET region, and a second fin in a finFET...
US-9,870,951 Method of fabricating semiconductor structure with self-aligned spacers
A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The...
US-9,870,950 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of...
US-9,870,949 Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the...
US-9,870,948 Forming insulator fin structure in isolation region to support gate structures
A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active...
US-9,870,947 Method for collective (wafer-scale) fabrication of electronic devices and electronic device
Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate...
US-9,870,946 Wafer level package structure and method of forming same
An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first...
US-9,870,945 Crystalline layer stack for forming conductive layers in a three-dimensional memory structure
A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline...
US-9,870,944 Back-end-of-line (BEOL) interconnect structure
A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the...
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