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Patent # Description
US-9,870,336 Implementing sideband control structure for PCIE cable cards and IO expansion enclosures
A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE)...
US-9,870,335 Implementing sideband control structure for PCIE cable cards and IO expansion enclosures
A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE)...
US-9,870,334 Dense, nested arrangement of multiple peripheral component interconnect express (PCIe) cards within a thin...
An information handling system (IHS) server volume includes at least two pairs of flexible peripheral component interconnect express (PCIe) media for connecting...
US-9,870,333 Instrumentation chassis including integrated accelerator module
A peripheral component interconnect express (PCIe) eXtensions for instrumentation (PXIe) chassis includes a backplane, multiple peripheral slots, a mezzanine...
US-9,870,332 Protocol conversion system
An Ethernet/Fiber Channel conversion system includes a chassis having a first end and a second end that is located opposite the chassis from the first end. An...
US-9,870,331 Interface circuit
Devices and methods are provided where a first signal and a second signal are received. The second signal may be a single-ended signal and may be selectively...
US-9,870,330 Methods and systems for filtering collected QOS data for predicting an expected range for future QOS data
Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes from a storage operating system of a storage system are...
US-9,870,329 Techniques for escalating interrupts in a data processing system
A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of...
US-9,870,328 Managing buffered communication between cores
Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering...
US-9,870,327 Message-based memory access apparatus and access method thereof
A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command...
US-9,870,326 Transfer apparatus, transfer system, and non-transitory computer readable medium
A transfer apparatus includes first and second communication paths, an accepting unit, a registration unit, an acquisition unit, and a transfer unit. The...
US-9,870,325 Common die implementation for memory devices with independent interface paths
A memory device includes at least two independent interface paths, an interface path including multiple memory banks. The memory device can selectively operate...
US-9,870,324 Isolating guest code and data using multiple nested page tables
A hypervisor provides a guest operating system with a plurality of protection domains, including a root protection domain and one or more secure protection...
US-9,870,323 Thresholding task control blocks for staging and destaging
For thresholding task control blocks (TCBs) for staging and destaging, a first tier of TCBs are reserved for guaranteeing a minimum number of TCBs for staging...
US-9,870,322 Memory mapping for object-based storage devices
In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into...
US-9,870,321 Data storage device and flash memory control method
A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a...
US-9,870,320 Method for dynamically storing a flash translation layer of a solid state disk module
A shared memory is initially set in the solid state module. A command for accessing information is received. The translation time of the flash translation layer...
US-9,870,319 Multibank queuing system
Data items to be stored in a queue are received, where the queue is distributed among a plurality of memory banks. The data items are distributed among the...
US-9,870,318 Technique to improve performance of memory copies and stores
A system and method for efficiently relocating and initializing a block of memory of the computer system. For data initialization and data relocation, multiple...
US-9,870,317 Incremental class unloading in a region-based garbage collector
A technique for incrementally unloading classes using a region-based garbage collector is described. One aspect of such a technique includes maintaining a...
US-9,870,316 Bidirectional counter in a flash memory
A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update...
US-9,870,315 Memory and processor hierarchy to improve power efficiency
A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are...
US-9,870,314 Update testing by build introspection
The present disclosure provides new and innovative methods and systems for ordering tests in an application update environment. For example, an update to an...
US-9,870,313 Unit-level formal verification for vehicular software systems
According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software...
US-9,870,312 Generating reusable testing procedures
A selection of a plurality of graphical user interface (GUI) components of a GUI is received. The selection is received so that the GUI can be tested....
US-9,870,311 Mock object generation
The disclosure is generally directed towards automatically generating a mock object from a description of a real object, such as for use in testing. Mock object...
US-9,870,310 Data providers for annotations-based generic load generator
A generic transaction generator framework for testing a network-based production service may work in conjunction with a product-specific transaction creator...
US-9,870,309 Variable tracking in program debugging
A method and system for structuring program code to implement program debugging of the program code using tracking of variables. A first variable to be tracked...
US-9,870,308 Debugging of prefixed code
A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which...
US-9,870,307 Regression testing of software services
Techniques are provided for mocking downstream services while regression testing a service. In one technique a version of a service processes a request, during...
US-9,870,306 Exception prediction before an actual exception during debugging
An approach is provided for predicting an exception during debugging of software code before the debugging encounters the exception. A number of lines X is...
US-9,870,305 Debugging of prefixed code
A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which...
US-9,870,304 System for verifying historical artifacts in disparate source control systems
A system for verifying historical artifacts in disparate source control systems. The system comprising a computer processor, a computer-readable hardware...
US-9,870,303 Monitoring and correlating a binary process in a distributed business transaction
A dynamic monitoring process begins with configuring a start and end method to be monitored. The dynamic monitoring process may intercept both the start and end...
US-9,870,302 Providing data to a user interface for performance monitoring
A method, system, and computer readable storage medium for providing data to a user interface for performance monitoring are disclosed, in which an a data...
US-9,870,301 High-speed debug port using standard platform connectivity
A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in...
US-9,870,300 Logged event frequency visualization
Embodiments of the present invention provide a method, system and computer program product for logged event frequency visualization. In an embodiment of the...
US-9,870,299 Logic circuit for the gathering of trace data
A logic circuit comprises a plurality of functional logic units each having an independent clock signal and a trace bus for carrying trace data. A trace...
US-9,870,298 Application resource utilization management
Methods and systems for automatically identifying an application that is experiencing performance problems caused by a resource utilization event may include...
US-9,870,297 Optimization of power and computational density of a data center
Techniques for optimizing power and computational density of data centers are described. According to various embodiments, a benchmark test is performed by a...
US-9,870,296 Evaluating system performance
A method and system for use in evaluating system performance is disclosed. In at least one embodiment, the method and system comprises collecting system...
US-9,870,295 Automation of workflow creation and failure recovery
A system includes a processor and a non-transitory computer-readable medium. The non-transitory computer-readable medium comprises instructions executable by...
US-9,870,294 Visualization of behavior clustering of computer applications
Dimensionality reduction, such as principal component analysis, may be performed against a time series of performance observations for a computer application. A...
US-9,870,293 Memory device performing post package repair (PPR) operation
A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a...
US-9,870,292 Configurationless redundancy
A method for configuring components in a computing system. A selected one of the components is designated as a primary component, the other components thereby...
US-9,870,291 Snapshotting shared disk resources for checkpointing a virtual machine cluster
Embodiments are directed to backing up a virtual machine cluster and to determining virtual machine node ownership prior to backing up a virtual machine...
US-9,870,290 System and method for hybrid kernel and user-space checkpointing using a character device
A system, method, and computer readable medium for hybrid kernel-mode and user-mode checkpointing of multi-process applications. The computer readable medium...
US-9,870,289 Notifying a backup application of a backup key change
A notifying system to notify a backup application of a backup key change includes receiving, from a backup application, a request to associate with a backup...
US-9,870,288 Container-based processing method, apparatus, and system
A container-based processing method includes: when a container state needs to be backed up, determining that content of a first control group file in at least...
US-9,870,287 Volume duplication
A method, computer program product, and computing system for receiving a point-in-time copy command for a virtual volume exposed within a storage virtualization...
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