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Patent # Description
US-9,882,031 Method of manufacturing a horizontal gate-all-around transistor having a fin
A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a...
US-9,882,030 Method to enhance FinFET device performance with channel stop layer depth control
A method for manufacturing a fin-type semiconductor device includes providing a semiconductor structure comprising a plurality of fins, and a plurality of...
US-9,882,029 Semiconductor device including Fin-FET and manufacturing method thereof
A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer...
US-9,882,028 Pitch split patterning for semiconductor devices
A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second...
US-9,882,027 Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having...
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For...
US-9,882,026 Method for forming a nanowire structure
Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a...
US-9,882,025 Methods of simultaneously forming bottom and top spacers on a vertical transistor device
One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure...
US-9,882,024 Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin;...
US-9,882,023 Sidewall spacers for self-aligned contacts
A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first...
US-9,882,022 Method for manufacturing transistor with SiCN/SiOCN multilayer spacer
A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate...
US-9,882,021 Planar III-V field effect transistor (FET) on dielectric layer
A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in...
US-9,882,020 Cascode configured semiconductor component
In accordance with an embodiment, a cascode connected semiconductor component and a method for manufacturing the cascode connected semiconductor component are...
US-9,882,019 Compound varactor
The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base...
US-9,882,018 Semiconductor device with a tunneling layer having a varying nitrogen concentration, and method of...
A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer...
US-9,882,017 Thin oxide formation by wet chemical oxidation of semiconductor surface when the one component of the oxide is...
A semiconductor device is provided, which comprises a semiconductor structure having a surface, the semiconductor structure comprising a material whose oxide is...
US-9,882,016 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,882,015 Transistors, semiconductor devices, and electronic devices including transistor gates with conductive elements...
A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder...
US-9,882,014 Semiconductor device and method for manufacturing the same
The semiconductor device includes an oxide semiconductor; a source electrode and a drain electrode in contact with the oxide semiconductor; a gate insulating...
US-9,882,013 Semiconductor device and manufacturing method thereof
Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an...
US-9,882,012 Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions
A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel...
US-9,882,011 Semiconductor device with reduced parasitic drain-gate capacitance and method of manufacturing the same
A semiconductor device having electrodes of three or more levels, includes: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate;...
US-9,882,010 Silicon carbide substrate and method for producing silicon carbide substrate
A silicon carbide substrate includes a Si substrate (silicon substrate), a SiC base film (silicon carbide base film) which is stacked on the Si substrate and...
US-9,882,009 High resistance layer for III-V channel deposited on group IV substrates for MOS transistors
Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as...
US-9,882,008 Graphene FET with graphitic interface layer at contacts
A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on...
US-9,882,007 Handle for semiconductor-on-diamond wafers and method of manufacture
Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers (401) to a carrier (407) are disclosed that flatten said wafers and...
US-9,882,006 Silicon germanium fin channel formation
A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying...
US-9,882,005 Fully depleted silicon-on-insulator device formation
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described....
US-9,882,004 Semiconductor device having asymmetrical source/drain
A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper...
US-9,882,003 Device and system of a silicon controlled rectifier (SCR)
Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may...
US-9,882,002 FinFET with an asymmetric source/drain structure and method of making same
Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor...
US-9,882,001 Materials and methods for the preparation of nanocomposites
Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method...
US-9,882,000 Wrap around gate field effect transistor (WAGFET)
A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer...
US-9,881,999 Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as "nanowires",...
US-9,881,998 Stacked nanosheet field effect transistor device with substrate isolation
Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers....
US-9,881,997 Semiconductor device and manufacturing method of semiconductor device
A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active portion....
US-9,881,996 Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a...
US-9,881,995 MOSFET having dual-gate cells with an integrated channel diode
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region....
US-9,881,994 Insulated gate bipolar transistor and manufacturing method therefor
An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is...
US-9,881,993 Method of forming semiconductor structure with horizontal gate all around structure
A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a...
US-9,881,992 Semiconductor integrated circuit device having with a reservoir capacitor
A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in...
US-9,881,991 Capacitor and method of forming a capacitor
A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially...
US-9,881,990 Integrated inductor for integrated circuit devices
A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or...
US-9,881,989 Flexible display panel and display device
The embodiments of the present invention provide a flexible display panel and a display device comprising the flexible display panel. The flexible display panel...
US-9,881,988 Flexible display
A flexible display is disclosed. In one aspect, the flexible display includes a substrate, a gate insulating layer formed over the substrate, an interlayer...
US-9,881,987 Organic light emitting diode display device and method for manufacturing the same
An OLED display device includes a display area of a substrate to display images; a non-display area surrounding the display area and applying signals to pixels...
US-9,881,986 Thin film transistor substrate and display using the same
Provided are a thin film transistor (TFT) substrate and a display using the same. A display includes: a first TFT, including: a polycrystalline semiconductor...
US-9,881,985 OLED device, AMOLED display device and method for manufacturing same
Embodiments of the invention disclose an OLED device, an AMOLED display device and a method for manufacturing the AMOLED display device. the AMOLED display...
US-9,881,984 Organic electro-luminescent display device
An organic EL display device includes an inorganic insulating film including a contact part as an opening where a contact electrode made of a conductive film is...
US-9,881,983 Organic light-emitting diode display
An OLED display is disclosed. A plurality of signal lines are formed over a substrate, and a plurality of pixels are formed over the substrate in a matrix form...
US-9,881,982 Organic light emitting display
An organic light emitting display includes a substrate including a first region and a second region adjacent to the first region, a plurality of first organic...
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