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Patent # Description
US-9,881,928 Method for producing one-time-programmable memory cells and corresponding integrated circuit
An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of...
US-9,881,927 CMOS-compatible polycide fuse structure and method of fabricating same
CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor...
US-9,881,926 Static random access memory (SRAM) density scaling by using middle of line (MOL) flow
A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide...
US-9,881,925 Mirror contact capacitor
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top...
US-9,881,924 Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and...
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas...
US-9,881,923 Floating body transistors and memory arrays comprising floating body transistors
Some embodiments include a floating body transistor which has a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a...
US-9,881,922 Semiconductor device and method
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer...
US-9,881,921 Fabricating a dual gate stack of a CMOS structure
A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel...
US-9,881,920 Semiconductor device and method of manufacturing the same
A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the...
US-9,881,919 Well and punch through stopper formation using conformal doping
A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant...
US-9,881,918 Forming doped regions in semiconductor strips
A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor...
US-9,881,917 Semiconductor device and method of manufacturing the same
A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second...
US-9,881,916 Semiconductor device
To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT...
US-9,881,915 Power FET with a resonant transistor gate
A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more...
US-9,881,914 Electrostatic discharge protection device
An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a...
US-9,881,913 Bipolar SCR
A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second...
US-9,881,912 Semiconductor device, inverter circuit, driving device, vehicle, and elevator
A semiconductor device according to an embodiment includes a plurality of circuit units, and each of the circuit units includes, a first electrode, a second...
US-9,881,911 Electronic system having increased coupling by using horizontal and vertical communication channels
An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for...
US-9,881,910 Apparatuses and methods for forming die stacks
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base...
US-9,881,909 Method for attaching a semiconductor die to a carrier
A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a...
US-9,881,908 Integrated fan-out package on package structure and methods of forming same
An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to...
US-9,881,907 Aggregation of semiconductor devices and the method thereof
An aggregation of semiconductor devices comprises a first layer, a second layer adhered to the first layer, and a plurality of semiconductor devices arranged...
US-9,881,906 Semiconductor module
According to one embodiment, a semiconductor module includes: a substrate; a first interconnect layer provided on the substrate; a plurality of first...
US-9,881,905 Electronic packages with three-dimensional conductive planes, and methods for fabrication
An electronic package includes an adhesion layer between a first substrate and a second substrate. The adhesion layer is patterned to define openings aligned...
US-9,881,904 Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and...
A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer...
US-9,881,903 Package-on-package structure with epoxy flux residue
A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is...
US-9,881,902 Semiconductor package, semiconductor device using the same and manufacturing method thereof
A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first...
US-9,881,901 Stacked package device and method for fabricating the same
A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of...
US-9,881,900 Semiconductor device
A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate...
US-9,881,899 Organic light-emitting device and organic display device
An organic light-emitting device having light-emitting portions arranged in two directions along a substrate main surface. Each light-emitting portion, in a...
US-9,881,898 System in package process flow
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends...
US-9,881,897 Manufacturing method of ultra-thin semiconductor device package assembly
A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is...
US-9,881,896 Advanced chip to wafer stacking
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips,...
US-9,881,895 Wire bonding methods and systems incorporating metal nanoparticles
Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in...
US-9,881,894 Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around...
US-9,881,893 Apparatus for removing chip
The present disclosure provides an apparatus for removing a chip, including: a loading station; a heating head arranged to soften an anisotropic conductive film...
US-9,881,892 Integrated circuit device
An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure,...
US-9,881,891 Method of forming three-dimensional wire loops and wire loops formed using the method
The invention provides a method of bonding wire between first and second bonding points with a bonding tool. It comprises the steps of forming a first bond at...
US-9,881,890 Semiconductor module, bonding jig, and manufacturing method of semiconductor module
A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including...
US-9,881,889 Chip package and method for fabricating the same
A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the...
US-9,881,888 Manufacturing method of interconnect structure
A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on...
US-9,881,886 Semiconductor device assemblies including intermetallic compound interconnect structures
A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the...
US-9,881,884 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second...
US-9,881,883 Electronic device with microfilm antenna and related methods
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
US-9,881,882 Semiconductor package with three-dimensional antenna
A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of...
US-9,881,881 Conductive seal ring for power bus distribution
A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a...
US-9,881,880 Tamper-proof electronic packages with stressed glass component substrate(s)
Tamper-proof electronic packages and fabrication methods are provided which include a glass substrate. The glass substrate is stressed glass with a...
US-9,881,879 Power semiconductor module
In a power semiconductor module, the 0.2% yield strength of solder under a lead terminal that bonds the lead terminal and a semiconductor element is set to be...
US-9,881,878 Semiconductor device and method of producing semiconductor device
A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element...
US-9,881,877 Electronic circuit package using composite magnetic sealing material
Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold resin...
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