Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,881,876 Semiconductor device having conductive shield layer
A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on...
US-9,881,875 Electronic module and method of making the same
A method of manufacturing electronic module is provided. The method can perform selective partial molding by forming the tapes in a predetermined area on the...
US-9,881,874 Forming method of superposition checking mark, manufacturing method of a semiconductor device and semiconductor...
According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with...
US-9,881,873 Fan-out semiconductor package
A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an...
US-9,881,872 Method for fabricating a local interconnect in a semiconductor device
A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second...
US-9,881,871 Schemes for forming barrier layers for copper in interconnect structures
A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring...
US-9,881,870 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over...
US-9,881,869 Middle of the line integrated efuse in trench EPI structure
A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric...
US-9,881,868 Semiconductor device
A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first...
US-9,881,867 Conductive connection structure having stress buffer layer
A conductive connection structure includes a semiconductor substrate, a conductive pillar, and a stress buffer layer. The conductive pillar is in the...
US-9,881,865 Semiconductor devices including electrically isolated patterns and method of fabricating the same
A method of forming a composite dielectric material can be provided by performing a first deposition cycle to form a first dielectric material and performing a...
US-9,881,864 Method for fabricating semiconductor package and semiconductor package using the same
Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the...
US-9,881,863 Semiconductor packages and methods of packaging semiconductor devices
A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads...
US-9,881,862 Top side cooling for GaN power device
A packaged semiconductor includes an electrically insulating encapsulant having opposite facing first and second planar sides. A thermally conductive substrate...
US-9,881,861 Wiring substrate
A Wiring substrate includes a substrate body that is formed from ceramics, and that includes a front surface, a back surface, and side surfaces positioned...
US-9,881,860 Method for producing waveguide substrate
To allow a metal film to have a sufficient thickness around a bottom surface of a non-through hole and prevent the metal film from being peeled from a substrate...
US-9,881,859 Substrate block for PoP package
A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate...
US-9,881,858 Solder bond site including an opening with discontinuous profile
Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least...
US-9,881,857 Pad design for reliability enhancement in packages
A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of...
US-9,881,856 Molded intelligent power module
An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a...
US-9,881,855 Semiconductor device and metering apparatus
A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that...
US-9,881,854 Cascode semiconductor package and related methods
A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically...
US-9,881,853 Semiconductor package having a source-down configured transistor die and a drain-down configured transistor die
A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first...
US-9,881,852 Semiconductor module
A semiconductor module of an electric power converter includes an IGBT and a MOSFET which are connected in parallel to each other and provided on the same lead...
US-9,881,851 Semiconductor device and method for producing semiconductor device
A semiconductor device includes a semiconductor substrate, a device layer located at an upper surface of the semiconductor substrate, an insulating layer...
US-9,881,850 Package structures and method of forming the same
Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The...
US-9,881,849 Method of forming an integrated circuit with heat-mitigating diamond-filled channels
An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer...
US-9,881,848 Thermal interface material on package
A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes...
US-9,881,847 Semiconductor structure having thermal backside core
A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes...
US-9,881,846 Semiconductor device
A semiconductor device includes: a semiconductor element; a laminated substrate including an insulating plate and a circuit board which is arranged on the front...
US-9,881,845 Electronic device, lid structure and package structure
An electronic device includes a transducer including a sensing area and a covering structure that covers the transducer. The covering structure includes a...
US-9,881,844 Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using...
An integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an...
US-9,881,843 Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,881,842 Wimpy and nominal semiconductor device structures for vertical finFETs
A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical...
US-9,881,841 Methods for fabricating integrated circuits with improved implantation processes
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having...
US-9,881,840 Method of fabricating gate electrode using a treated hard mask
A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask...
US-9,881,839 Forming a hybrid channel nanosheet semiconductor structure
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner...
US-9,881,838 Semiconductor devices having multiple gate structures and methods of manufacturing such devices
A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate...
US-9,881,837 Fin-like field effect transistor (FinFET) based, metal-semiconductor alloy fuse device and method of...
A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a...
US-9,881,836 Method for manufacturing semiconductor device
A method for manufacturing semiconductor devices comprises: applying a dual pulse power to the semiconductor device during metal electroplating a part of the...
US-9,881,835 Nanowire devices, systems, and methods of production
A method of depositing nanowires including generating wells disposed on a patterned conductive film. The patterned conductive film includes well-sites. The...
US-9,881,834 Contact openings and methods forming same
A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer....
US-9,881,833 Barrier planarization for interconnect metallization
A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on...
US-9,881,832 Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared...
US-9,881,831 Method for fabricating semiconductor device including fin shaped structure
A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench...
US-9,881,830 Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin...
US-9,881,829 Adhesive composition, laminate, and stripping method
An adhesive composition for temporarily attaching a substrate to a support plate which supports the substrate, including a thermoplastic resin and a release agent.
US-9,881,828 Wafer processing method
Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a...
US-9,881,827 Substrate treating apparatus and substrate treating method
An embodiment includes a substrate treating apparatus comprising: a tape supply member configured to supply a tape to be attached to a substrate; a tape...
US-9,881,826 Buffer station with single exit-flow direction
A buffer for use in semiconductor processing tools is disclosed. The buffer may be used to temporarily store wafers after processing operations are performed on...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.