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Patent # Description
US-9,887,142 Power semiconductor device
This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is...
US-9,887,141 TFT switch and method for manufacturing the same
A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal....
US-9,887,140 Wafer processing method
There is provided a wafer processing method for dividing a wafer having a plurality of devices formed in regions partitioned by a plurality of crossing division...
US-9,887,139 Integrated heterojunction semiconductor device and method for producing an integrated heterojunction...
A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical...
US-9,887,138 Semiconductor device
A semiconductor device includes first and second MIS transistors and a dummy element. The first MIS transistor includes a first gate insulating film which...
US-9,887,137 FinFET devices and methods of forming
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a...
US-9,887,136 Semiconductor devices, FinFET devices, and methods of forming the same
Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first...
US-9,887,135 Methods for providing variable feature widths in a self-aligned spacer-mask patterning process
A method includes forming a first mandrel layer above a first process layer. A first implant region is formed in the first mandrel layer. The first mandrel...
US-9,887,134 Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices
Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of...
US-9,887,133 Two-dimensional self-aligned super via integration on self-aligned gate contact
Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal...
US-9,887,132 Method for forming semiconductor structure
A semiconductor structure and a method for forming the semiconductor structure are provided. In various embodiments, the method for forming a semiconductor...
US-9,887,131 Semiconductor device having a Pd-containing adhesion layer
According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing...
US-9,887,130 FinFET device and method of forming the same
Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate...
US-9,887,129 Semiconductor structure with contact plug
The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a...
US-9,887,128 Method and structure for interconnection
The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes forming a first low-k...
US-9,887,127 Interconnection lines having variable widths and partially self-aligned continuity cuts
A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The...
US-9,887,126 Structure of dual damascene structures having via hole and trench
A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
US-9,887,125 Method of manufacturing a semiconductor device comprising field stop zone
A method of manufacturing a semiconductor device includes forming a field stop zone by irradiating a portion of a semiconductor body with a laser beam through a...
US-9,887,124 Method for producing a composite structure
A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support...
US-9,887,123 Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method
A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a...
US-9,887,122 Method and apparatus for processing wafer-shaped articles
In an apparatus for treating a wafer-shaped article, a spin chuck is configured to hold a wafer-shaped article of a predetermined diameter. A non-rotating plate...
US-9,887,121 Protective cover for electrostatic chuck
A protective cover for an electrostatic chuck may include a conductive wafer and a plasma resistant ceramic layer on at least one surface of the conductive...
US-9,887,120 Apparatus for treating surfaces of wafer-shaped articles
A rotary chuck for processing wafer-shaped articles comprises a chuck body having a series of gripping pins that are movable by sliding horizontally and in...
US-9,887,119 Multi-chip package assembly
Methods of bonding chips to a substrate and transfer wafers used for such bonding include bonding chips to a first support wafer by a first adhesive layer. The...
US-9,887,118 Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin...
A wafer processing laminate including a support, a temporary adhesive material layer formed on the support, and a wafer laminated on the temporary adhesive...
US-9,887,117 Electrostatic chuck and semiconductor-liquid crystal manufacturing apparatus
An electrostatic chuck includes a base plate including a penetration hole, a placing table arranged on the base plate, and including an electrode at a position...
US-9,887,116 Substrate storing container
The tip face 411 of the base portion 41 inserted into the retaining groove 321 and the groove bottom face 322 have a positional relationship of facing each...
US-9,887,115 Substrate processing apparatus, cover opening and closing mechanism,shielding mechanism, and method for purging...
Provided is a substrate processing apparatus that can suppress the amount of inert gas and dry gas used and also can prevent reductions in throughput. A...
US-9,887,114 IC cartridge
An IC cartridge is provided, which includes: a cartridge body provided with hollowed-out parts, and an ejection mechanism including a substrate and projected...
US-9,887,113 Semiconductor chip tray
A semiconductor chip tray is provided that includes a support plate, a first protruding portion, a second protruding portion and a recess. The first protruding...
US-9,887,112 Inkjet coating device and coating method
An inkjet coating device comprises a support board and a sprinkler head. The support board is provided for placing the glass plate, the sprinkler head comprises...
US-9,887,111 Die mounting system and die mounting method
In a die mounting system in which a die supply device is set on a component mounter and dies supplied from a die supply device are mounted on a circuit board by...
US-9,887,110 Substrate warpage control using temper glass with uni-directional heating
A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a...
US-9,887,109 Plasma etching method and plasma etching apparatus
A plasma etching method includes a holding step of holding a substrate, a processing gas supplying step of supplying processing gas to a space between the...
US-9,887,108 Gas supply device and substrate processing apparatus
A shower head 13 (gas supply device) of supplying a processing gas and an additional gas from a processing gas supply source and an additional gas source,...
US-9,887,107 Methodologies for rinsing tool surfaces in tools used to process microelectronic workpieces
Rinsing methodologies and components to accomplish rinsing of tool surfaces in tools that are used to process one or more microelectronic workpieces. The...
US-9,887,106 Ejection inspection apparatus and substrate processing apparatus
An ejection inspection part of a substrate processing apparatus includes a light emitting part and an imaging part. The light emitting part emits light along a...
US-9,887,105 Manufacturing method of semiconductor device
An object of the present invention is to improve the reliability and productivity of a semiconductor device by suppressing generation of a resin burr in a...
US-9,887,104 Electronic package and method of connecting a first die to a second die to form an electronic package
Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package...
US-9,887,103 Semiconductor device and method of adaptive patterning for panelized packaging
An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper...
US-9,887,102 Method for manufacturing multi-chip package
A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically...
US-9,887,101 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing...
US-9,887,100 Methods of forming semiconductor devices and structures thereof
Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes...
US-9,887,099 Pattern forming method capable of minimizing deviation of an inversion pattern
A method includes: forming a metal oxide film on a substrate including an etching target film and a metal pattern formed thereon, and forming an oxide film...
US-9,887,098 Method for manufacturing integrated circuit device
According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film,...
US-9,887,097 Technique to deposit sidewall passivation for high aspect ratio cylinder etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate...
US-9,887,096 Differential silicon oxide etch
A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch....
US-9,887,095 System and method for an etch process with silicon concentration control
The present disclosure provides one embodiment of an etch system. The etch system includes a tank designed to hold an etch solution for etching; a silicon...
US-9,887,094 Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device
One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer...
US-9,887,093 Semiconductor device manufacturing method
A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a...
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