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Patent # Description
US-9,893,092 Thin-film transistor array substrate having oxide semiconductor with channel region between conductive regions
Provided is a method of manufacturing TFT substrate, the method including: forming a first conductive layer and a gate electrode; forming a gate insulating...
US-9,893,091 Array substrate and fabricating method thereof, display panel and display apparatus
An array substrate and a fabricating method thereof, a display panel and a display apparatus are disclosed. The array substrate includes a base substrate and a...
US-9,893,090 Array substrate and fabrication method thereof, and display device
An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises a gate line and a data line intersecting...
US-9,893,089 Semiconductor device and manufacturing method thereof
As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number...
US-9,893,088 Thin film transistor device, method for manufacturing same and display device
A thin film transistor device including: a substrate; a gate electrode; an electrode pair composed of a source electrode and a drain electrode; a channel layer;...
US-9,893,087 Thin film transistor substrate, display apparatus including thin film transistor substrate, method of...
A thin film transistor TFT substrate includes a substrate, a first conductive pattern that extends on the substrate in a first direction, a second conductive...
US-9,893,086 Contact punch through mitigation in SOI substrate
A method of forming a contact to mitigate punch through in SOI substrates is disclosed. The method may include providing an active region in SOI substrate...
US-9,893,085 Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture
A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates...
US-9,893,084 U-shaped common-body type cell string
A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped...
US-9,893,083 Elevationally-extending strings of memory cells individually comprising a programmable charge storage...
A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the...
US-9,893,082 Semiconductor memory device and method of fabricating the same
A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A...
US-9,893,081 Ridged word lines for increasing control gate lengths in a three-dimensional memory device
After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater...
US-9,893,080 Semiconductor device having a diverse shaped columnar portion
A surface area of a transverse cross section of an upper portion of a columnar portion is greater than a surface area of a transverse cross section of a lower...
US-9,893,079 Semiconductor memory device
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation...
US-9,893,078 Semiconductor memory device
A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that...
US-9,893,077 Memory device and method of manufacturing the same
A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first...
US-9,893,076 Access transistor of a nonvolatile memory device and method for fabricating same
A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer...
US-9,893,075 Semiconductor memory device
A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through...
US-9,893,074 Semiconductor device
A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The...
US-9,893,073 Semiconductor nonvolatile memory element
A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile...
US-9,893,072 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-9,893,071 Semiconductor device and method for forming the same
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region...
US-9,893,070 Semiconductor device and fabrication method therefor
A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of...
US-9,893,069 Semiconductor device having buried gate structure and method of fabricating the same
A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the...
US-9,893,068 Method for manufacturing a semiconductor device
To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a...
US-9,893,067 Memory device having electrically floating body transistor
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least...
US-9,893,066 Semiconductor transistor device and method for fabricating the same
A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a...
US-9,893,065 Semiconductor integrated circuit
A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an...
US-9,893,064 Integrated circuit device and method of manufacturing the same
An integrated circuit device includes a substrate, first and second fin-type active areas which extend in a first direction on the substrate, first and second...
US-9,893,063 Special construct for continuous non-uniform active region FinFET standard cells
Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having...
US-9,893,062 Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second)...
US-9,893,061 Multi-Fin device and method of making same
A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A...
US-9,893,060 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device...
US-9,893,059 ROM chip manufacturing structures
An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include...
US-9,893,058 Method of manufacturing a semiconductor device having reduced on-state resistance and structure
A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first...
US-9,893,057 Monolithically integrated semiconductor switch, particularly circuit breaker
A monolithically integrated semiconductor switch, particularly a circuit breaker, has regenerative turn-off behavior. The semiconductor switch has two...
US-9,893,056 Multi-layer semiconductor device structure
One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a...
US-9,893,055 Semiconductor device including an insulated gate bipolar transistor and a circuit configured to control the...
A semiconductor device includes a first element portion including an IGBT and a second element portion including a circuit that controls the IGBT on the same...
US-9,893,054 ESD protection circuit cell
A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an...
US-9,893,053 Semiconductor device including ESD protection circuit
A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied...
US-9,893,052 FinFET-based ESD devices and methods for forming the same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is...
US-9,893,051 LED chip having ESD protection
Disclosed herein is a light emitting diode chip having ESD protection. An exemplary embodiment provides a flip-chip type light emitting diode chip, which...
US-9,893,050 ESD protection structure
An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well...
US-9,893,049 Electrostatic discharge protection device
The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region,...
US-9,893,048 Passive-on-glass (POG) device and method
A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via...
US-9,893,047 Manufacture of wafer--panel die package assembly technology
Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional...
US-9,893,046 Thinning process using metal-assisted chemical etching
Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted...
US-9,893,045 Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of...
US-9,893,044 Wafer-level underfill and over-molding
A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring...
US-9,893,043 Method of manufacturing a chip package
Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip...
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