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Patent # Description
US-9,892,990 Semiconductor package lid thermal interface material standoffs
Semiconductor package lid thermal interface material standoffs are disclosed and may include a substrate, a semiconductor die bonded to the substrate, a package...
US-9,892,989 Wafer-level chip scale package with side protection
A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer...
US-9,892,988 Semiconductor packaging structure and manufacturing method for the same
A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric...
US-9,892,987 Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
US-9,892,986 Packaged wafer manufacturing method and device chip manufacturing method
Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each...
US-9,892,985 Semiconductor device and method for manufacturing the same
One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least...
US-9,892,984 Embedded electronic packaging and associated methods
An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body...
US-9,892,983 Apparatus for forming a thin layer and method of forming a thin layer on a substrate using the same
An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form...
US-9,892,982 Method for controlling exhaust flow in wafer processing module
Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes placing the wafer into a processing assembly and heating...
US-9,892,981 Method and apparatus for depositing phosphor on semiconductor-light emitting device
A method and apparatus for depositing a phosphor using transfer molding. The method includes: forming a plurality of light-emitting devices on a wafer and...
US-9,892,980 Fan-out panel level package and method of fabricating the same
A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with...
US-9,892,979 Non-destructive dielectric layer thickness and dopant measuring method
A semiconductor device or article includes a substrate including a feature and divided into a feature region in which the feature is formed and a pad region in...
US-9,892,978 Forming a CMOS with dual strained channels
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and...
US-9,892,977 FinFET and method of forming fin of the FinFET
A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first...
US-9,892,976 Forming a hybrid channel nanosheet semiconductor structure
A nanosheet semiconductor structure includes a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material...
US-9,892,975 Adjacent strained <100> NFET fins and <110> PFET fins
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel...
US-9,892,974 Vertical power MOSFET and methods of forming the same
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and...
US-9,892,973 Stress memorization technique for strain coupling enhancement in bulk finFET device
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
US-9,892,972 3D semiconductor device and structure
A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal...
US-9,892,971 Crack prevent and stop for thin glass substrates
A method of forming a 3D crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and...
US-9,892,970 Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side...
US-9,892,969 Process of forming an electronic device
A process of forming an electronic device includes providing a substrate having a major surface; etching a portion of a the substrate to define a trench...
US-9,892,968 Semiconductor device having a dummy portion, method for manufacturing the semiconductor device, method for...
There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a...
US-9,892,967 Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate...
US-9,892,966 Metal only post-mask ECO for integrated circuit
A method of designing a layout of a metallization stack of an integrated circuit (IC), where the stack includes metal layers having patterned metal features....
US-9,892,965 Cu wiring manufacturing method and Cu wiring manufacturing system
In a Cu wiring manufacturing method for manufacturing Cu wiring that fills a recess formed in a predetermined pattern on a surface of an interlayer insulating...
US-9,892,964 Gap-fill polymer for filling fine pattern gaps and method for fabricating semiconductor device using the same
A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (low-k) and excellent gap filling properties, may consist of a compound...
US-9,892,963 Device and method for reducing contact resistance of a metal
A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a...
US-9,892,962 Wafer level chip scale package interconnects and methods of manufacture thereof
A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an...
US-9,892,961 Air gap spacer formation for nano-scale semiconductor devices
Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for...
US-9,892,960 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an...
US-9,892,959 Method for patterning mesoporous inorganic oxide film, and electric device including mesoporous inorganic oxide...
Provided are a method for patterning a mesoporous inorganic oxide film, the method including a step of forming a mesoporous inorganic oxide film using a...
US-9,892,958 Contact module for optimizing emitter and contact resistance
An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact...
US-9,892,957 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The...
US-9,892,956 Wafer positioning pedestal for semiconductor processing
An assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for...
US-9,892,955 Substrate holding/rotating device, substrate processing apparatus including the same, and substrate processing...
This substrate holding/rotating device includes an opening magnet forming a predetermined magnetic field generation region through which each movable pin...
US-9,892,954 Wafer processing system using multi-zone chuck
A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to...
US-9,892,953 Substrate gripping apparatus
The present invention relates to a substrate gripping apparatus includes a base, a plurality of support posts which are vertically movable relative to the base,...
US-9,892,952 Wafer level flat no-lead semiconductor packages and methods of manufacture
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a...
US-9,892,951 Method of controlling adherence of microparticles to substrate to be processed, and processing apparatus
A method of controlling adherence of microparticles to a substrate to be processed includes applying voltage to an electrostatic chuck configured to...
US-9,892,950 Ceramic member, member for semiconductor manufacturing apparatus, and method for manufacturing ceramic member
A ceramic member 30 according to the present invention includes a ceramic base 32, which contains a solid solution Mg(Al)O(N) in which Al and N components are...
US-9,892,949 Imprint method, imprint apparatus, and article manufacturing method
An imprint apparatus forms a pattern of an imprint material on a substrate by using a mold. A substrate holding unit holds the substrate by a suction force...
US-9,892,948 Wafer container having damping device
A wafer container is provided. The wafer container includes a pod base having a top surface and a bottom surface, a cassette disposed on the top surface, and a...
US-9,892,947 Sensor system for semiconductor manufacturing apparatus
A chamber monitoring system may include a parallel architecture in which a single sensor control system is coupled to a number of different processing chamber...
US-9,892,946 Processing apparatus and method
A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with...
US-9,892,945 Composite seal
The composite seal includes a metal member arranged on a first substrate side and an elastic member arranged on a second device side and capable of elastic...
US-9,892,944 Diodes offering asymmetric stability during fluidic assembly
Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in...
US-9,892,943 Method for laminating glass panels and vacuum lamination device using same
The present invention provides a method for laminating glass panels and a vacuum lamination device using the method. The method includes (1) providing a TFT...
US-9,892,942 Substrate processing apparatus
The present invention relates to a substrate processing apparatus. The substrate processing apparatus includes a chamber including a chamber body of which one...
US-9,892,941 Multi-zone resistive heater
Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support...
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