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Patent # Description
US-9,892,077 Camera control interface slave device to slave device communication
In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave...
US-9,892,076 Mobile hardware fob with device ecosystem for modular I/O extension devices
A fob device includes a portable housing below a size needed to accommodate an input/output component for providing access to a functionality of the fob device...
US-9,892,075 Policy driven storage in a microserver computing environment
An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O)...
US-9,892,074 System and method to support USB devices in an unsupported operating system in VDI environments
In certain information handling system environments, universal serial bus (USB) devices may be connected to a client and redirected to a server or other...
US-9,892,073 Bus addressing systems and methods using repurposed bits
Systems and methods for dynamically assigning unique identifiers for devices on a bus using repurposed bits. Dynamically assigned unique identifiers can be...
US-9,892,072 Transaction response modification within interconnect circuitry
Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry...
US-9,892,071 Emulating a remote direct memory access (`RDMA`) link between controllers in a storage array
Emulating a remote direct memory access (`RDMA`) link between controllers in a storage array, including: inserting, into a buffer utilized by a direct memory...
US-9,892,070 Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the...
Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor...
US-9,892,069 Posting interrupts to virtual processors
Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up...
US-9,892,068 Local internal discovery and configuration of individually selected and jointly selected devices
A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data...
US-9,892,067 Multiprocessor cache buffer management
In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for...
US-9,892,066 Dynamically adjusting read data return sizes based on interconnect bus utilization
A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core...
US-9,892,065 Adjustments of buffer credits for optimizing the number of retry operations and transfer ready operations
A control unit monitors a number of transfer ready operations and a number of retry operations during a monitoring period during communication with a plurality...
US-9,892,064 Universal input device
Embodiments of the invention are directed to input devices configured for use with computing devices. The present invention relates to methods and devices for...
US-9,892,063 Contention blocking buffer
In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory...
US-9,892,062 Information processing apparatus capable of backing up and restoring key for data encryption and method for...
An information processing apparatus includes a storage device configured to store data, an encryption chip configured to store an encryption key therein, a...
US-9,892,061 Direct memory access between an accelerator and a processor using a coherency adapter
Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to...
US-9,892,060 Identifying stale entries in address translation cache
A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing...
US-9,892,059 Multi-core shared page miss handler
Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system....
US-9,892,058 Centrally managed unified shared virtual address space
Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes...
US-9,892,057 Single double cuckoo hash
In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts...
US-9,892,056 Multi-core shared page miss handler
Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system....
US-9,892,055 Embedded device and memory management method thereof
An embedded device and a memory management method of the embedded device are provided. The embedded device includes a system memory and hardware memory. An...
US-9,892,054 Method and apparatus for monitoring system performance and dynamically updating memory sub-system settings...
A method and apparatus are disclosed to monitor system performance and dynamically update memory subsystem settings using software to optimize system...
US-9,892,053 Compaction for memory hierarchies
In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of...
US-9,892,052 Hybrid tracking of transaction read and write sets
Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are...
US-9,892,051 Method and apparatus for use of a preload instruction to improve efficiency of cache
A method can include executing a store instruction that instructs storing of data at an address and, in response to the store instruction, inserting a...
US-9,892,050 Multi-stage translation of prefetch requests
A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests...
US-9,892,049 Semiconductor device and method for prefetching to cache memory
A semiconductor device includes a processor, a memory, a plurality of tags, a plurality of ways each of which can store a plurality of data of consecutive...
US-9,892,048 Tuning global digests caching in a data deduplication system
Input data is partitioned into data chunks and digest values are calculated for each of the data chunks. The positions of similar repository data are found in a...
US-9,892,047 Multi-channel cache memory
A cache memory including: a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is...
US-9,892,046 Cache allocation based on quality-of-service information
A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by...
US-9,892,045 Methods to select segments of an evicted cache unit for reinsertion into the cache
A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of...
US-9,892,044 Methods to efficiently implement coarse granularity cache eviction
A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of...
US-9,892,043 Nested cache coherency protocol in a tiered multi-node computer system
A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a...
US-9,892,042 Method and system for implementing directory structure of host system
A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting...
US-9,892,041 Cache consistency optimization
Various methods and systems for optimizing cache consistency are disclosed. For example, one method involves writing data to a file during a write transaction....
US-9,892,039 Non-temporal write combining using cache resources
A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a...
US-9,892,038 Method, apparatus, and system for data caching
A data caching method is disclosed. The method comprises changing, according to an instruction, a cache value, corresponding to a key, in a cache on a volatile...
US-9,892,037 Efficient and secure direct storage device sharing in virtualized environments
A method, system and computer program product are disclosed for direct storage device sharing in a virtualized environment. In an embodiment, the method...
US-9,892,036 Apparatus and method of converting address and data of memory in a terminal
An apparatus and method of converting an address and data of a memory in a terminal. The apparatus includes a random key generator configured to generate a new...
US-9,892,035 Memory system for storing data corresponding to logical addresses into physical location accessible using...
A memory system supporting an interleaving operation including: a plurality of memory devices; and a controller suitable for detecting whether, among a...
US-9,892,034 Semiconductor device and operating method thereof
A semiconductor device includes a mapping table that stores a corresponding relation between a logical address defined on a basis of regions and a physical...
US-9,892,033 Management of memory units
A method for memory management, the method may include calculating, by a memory controller, an estimate of an effect of read operations on a first flash memory...
US-9,892,032 Management of random cache read operations
A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer....
US-9,892,031 Lock-free scalable free list
A plurality of free list data structures are maintained in a multi-processor computing system that each correspond to one processor of the multi-processor...
US-9,892,030 Method and apparatus for improving non-uniform memory access
A method, computer readable medium and apparatus for improving non-uniform memory access are disclosed. For example, the method divides a plurality of stream...
US-9,892,029 Apparatus and method for expanding the scope of systems management applications by runtime independence
An apparatus for automatic conversion of existing systems management software applications to run in multiple middleware runtime frameworks by automating the...
US-9,892,028 System and method for debugging of webcasting applications during live events
A system and method for debugging of live webcasting applications during live events is disclosed. The debugging system permits a user to quickly locate errors...
US-9,892,027 Event-driven software testing
A method may include determining sequence-execution constraints that constrain execution orders of a plurality of events of an event-driven software...
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