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| Patent # | Description |
|---|---|
| US-9,947,433 |
Thermoplastic resin composition and molded product using the same A thermoplastic resin composition includes 0.1 to 20 parts by weight of a carbon black relative to 100 parts by weight of a thermoplastic resin, wherein the... |
| US-9,947,432 |
Electrically conductive materials formed by electrophoresis A method of forming an electrically conductive composite is disclosed that includes the steps of providing a first dielectric material and a second conductive... |
| US-9,947,431 |
Anisotropic films templated using ultrasonic focusing An anisotropic composite film includes a plurality of effectively parallel lines of particles with a polymeric or other solid matrix. The composite films are... |
| US-9,947,430 |
Transparent conductive film comprising silver nanowires A transparent conductive film. The film comprises a transparent polymer comprising fused latex polymer particles. A plurality of nanowires comprising silver are... |
| US-9,947,429 |
Ag alloy film for reflecting electrode or wiring electrode, reflecting
electrode or wiring electrode, and Ag... An Ag alloy film used for a reflecting electrode or an interconnection electrode, the Ag alloy film exhibiting low electrical resistivity and high reflectivity... |
| US-9,947,428 |
Atomic beam source An atomic beam source includes a tubular cathode that includes an emission portion that includes an emission port through which an atomic beam can be emitted, a... |
| US-9,947,427 |
Scintillation crystal including a co-doped sodium halide, and a radiation
detection apparatus including the... A scintillation crystal can include a sodium halide that is co-doped with thallium and another element. In an embodiment, the scintillation crystal can include... |
| US-9,947,426 |
High voltage supply for compact radiation generator Disclosed is a radiation logging tool, comprising a tool housing; a compact generator that produces radiation; a power supply coupled to the compact generator;... |
| US-9,947,425 |
Method for reducing the radioactive contamination of the surface of a
component used in a nuclear reactor The invention relates to a method for reducing the radioactive contamination of the surface of a component used in a nuclear reactor, which component is in... |
| US-9,947,424 |
Coating type radiation-shielding material and radiation-shielding
elastomer material An object of the invention is to provide a radiation-shielding material that has a high radiation-shielding capability and can be easily coated, molded and... |
| US-9,947,423 |
Nanofuel internal engine A nanofuel engine including an inventive nanofuel internal engine, whereby nuclear energy is released in the working fluid and directly converted into useful... |
| US-9,947,422 |
Control method for a pressurized water nuclear reactor This invention relates to a control method for a pressurized water nuclear reactor, which comprises a core generating thermal power and means of acquiring... |
| US-9,947,421 |
Nuclear reactor with liquid metal coolant A nuclear reactor with a liquid metal coolant includes a housing having a separating shell disposed therein. In the annular space between the housing and the... |
| US-9,947,420 |
Magnetic field plasma confinement for compact fusion power In one embodiment, a fusion reactor includes a plurality of internal magnetic coils suspended within an enclosure, one or more center magnetic coils coaxial... |
| US-9,947,419 |
Apparatus and method for implementing design for testability (DFT) for
bitline drivers of memory circuits A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to... |
| US-9,947,418 |
Boosted channel programming of memory Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of... |
| US-9,947,417 |
Memory management method, memory storage device and memory controlling
circuit unit A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality... |
| US-9,947,416 |
Nonvolatile memory device, operating method thereof and memory system
including the same A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection... |
| US-9,947,415 |
Nonvolatile semiconductor memory device having a control circuit that
controls voltage applied to non-selected... A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control... |
| US-9,947,414 |
Nonvolatile memory device and operating method thereof An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit... |
| US-9,947,413 |
Method of initializing and programming 3D non-volatile memory device A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled... |
| US-9,947,412 |
Data writing method, memory control circuit unit and memory storage
apparatus A data writing method for a rewritable non-volatile memory module is provided. The method includes recording a plurality of characteristic parameters... |
| US-9,947,411 |
Memory system including a memory chip configured to receive an erase
suspend command and a program suspend... A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory... |
| US-9,947,410 |
Non-volatile semiconductor memory device A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality... |
| US-9,947,409 |
Flash memory In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a... |
| US-9,947,408 |
Semiconductor memory device that applies same voltage to two adjacent word
lines for access A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a... |
| US-9,947,407 |
Techniques for programming of select gates in NAND memory In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some... |
| US-9,947,406 |
Dynamic tag compare circuits employing P-type field-effect transistor
(PFET)-dominant evaluation circuits for... Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased... |
| US-9,947,405 |
Memristive dot product engine with a nulling amplifier A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a... |
| US-9,947,404 |
Resistive memory apparatus, selective write circuit therefor, and
operation method thereof A resistive memory apparatus may include a memory cell array and a selective write circuit. The memory cell array may include a plurality of resistive memory... |
| US-9,947,403 |
Method for operating non-volatile memory device and applications thereof A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process... |
| US-9,947,402 |
Method, system and device for non-volatile memory device operation Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed... |
| US-9,947,401 |
Peak current management in non-volatile storage Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high... |
| US-9,947,400 |
Methods for enhanced state retention within a resistive change cell A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell--that is, the tendency of the... |
| US-9,947,399 |
Updating resistive memory Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that... |
| US-9,947,398 |
Semiconductor memory device and operation method thereof A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and... |
| US-9,947,397 |
Crosspoint array decoder Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder... |
| US-9,947,396 |
Nonvolatile storage device and method of controlling the same To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage... |
| US-9,947,395 |
Programming techniques for non-volatile memories with charge trapping
layers Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a... |
| US-9,947,394 |
Nonvolatile memory device including page buffer and method for reading
data without a dumping process for... A nonvolatile memory device including a page buffer and a method of operating the nonvolatile memory device, the method including performing a first sensing... |
| US-9,947,393 |
Semiconductor integrated circuit device A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair... |
| US-9,947,392 |
Memory device sensing circuit A memory device includes a first memory array comprising a first bit cell configured to store a first logical state; and a reference signal provision (RSP)... |
| US-9,947,391 |
SRAM based physically unclonable function and method for generating a PUF
response A physically unclonable function (PUF) is implemented in a plurality of SRAM cells. In a method for generating a PUF response, a logic zero is first written to... |
| US-9,947,390 |
Structure and methods of operating two identical 4T random access memories
storing the same data The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory... |
| US-9,947,389 |
Single ended memory device A memory device includes a memory cell that is configured to store a data bit, comprising at least one read transistor that is configured to form either a... |
| US-9,947,388 |
Reduced swing bit-line apparatus and method Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more... |
| US-9,947,387 |
Systems and methods for reducing standby power in floating body memory
devices Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters... |
| US-9,947,386 |
Thermal aware data placement and compute dispatch in a memory system A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a... |
| US-9,947,385 |
Data sense amplification circuit and semiconductor memory device including
the same A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense... |
| US-9,947,384 |
Semiconductor device relating to generate target address to execute a
refresh operation A semiconductor device may be provided. The semiconductor device may include a target address storage circuit and a first row address generation circuit. The... |
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