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Patent # Description
US-1,000,2797 Chip integration including vertical field-effect transistors and bipolar junction transistors
Device structures and fabrication methods for a BiCMOS integrated circuit. A first fin and a second fin are formed on a semiconductor substrate. A gate...
US-1,000,2796 Dual epitaxial growth process for semiconductor device
A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first...
US-1,000,2795 Method and structure for forming vertical transistors with shared gates and separate gates
A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate...
US-1,000,2794 Multiple gate length vertical field-effect-transistors
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a...
US-1,000,2793 Sub-fin doping method
A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first...
US-1,000,2792 HDP fill with reduced void formation and spacer damage
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
US-1,000,2791 Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS
A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the...
US-1,000,2790 Mechanisms for forming semiconductor device structure with feature opening
A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a...
US-1,000,2789 High performance middle of line interconnects
A method for formation of multi-level contact structures with reduced contact resistance is provided. The contact resistance of the multi-level contact...
US-1,000,2788 Methods of fabricating semiconductor devices
Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern,...
US-1,000,2787 Staircase encapsulation in 3D NAND fabrication
Methods and apparatuses for depositing an encapsulation layer over a staircase structure during fabrication of a 3D NAND structure to prevent degradation of an...
US-1,000,2786 Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned...
US-1,000,2785 Air-gap assisted etch self-aligned dual Damascene
A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an...
US-1,000,2783 Method for manufacturing memory device
A method for manufacturing a memory device may include the following steps: preparing a first semiconductor, a second semiconductor, a first conductor, and a...
US-1,000,2782 ESC assembly including an electrically conductive gasket for uniform RF power delivery therethrough
A substrate processing apparatus for processing substrates comprises a processing chamber in which a substrate is processed. A process gas source is adapted to...
US-1,000,2781 Tool auto-teach method and apparatus
A substrate transport apparatus auto-teach system for auto-teaching a substrate station location, the system including a frame, a substrate transport connected...
US-1,000,2780 Method of manufacturing a semiconductor structure
A method of manufacturing a semiconductor structure includes providing a substrate, disposing a first semiconductive material over the substrate at a first...
US-1,000,2779 Thermal array system
A thermal array system is provided. The system includes a first thermal element and a second thermal element connected between a first node and a second node....
US-1,000,2778 Substrate cleaning apparatus
A substrate cleaning apparatus includes outer circumference supporting members 32 that support the outer circumference of a rotating substrate W, a swing...
US-1,000,2777 Substrate processing system and substrate processing method
Provided is a substrate processing system and a substrate processing method. The substrate processing system includes a polishing part for performing a Chemical...
US-1,000,2776 Wafer manufacturing cleaning apparatus, process and method of use
A cleaning wafer or substrate for use in cleaning, or in combination with, components of, for example, integrated chip manufacturing apparatus. The cleaning...
US-1,000,2775 Method of manufacturing semiconductor device
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then...
US-1,000,2774 Metal interconnect processing for a non-reactive metal stack
A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having...
US-1,000,2773 Method for selectively etching silicon oxide with respect to an organic mask
A method for selectively etching trenches in a silicon oxide containing layer with an organic planarization layer is provided. Processing the silicon oxide...
US-1,000,2772 Vapor phase etching of hafnia and zirconia
A method is described for vapor phase etching of oxide material including at least one of hafnia (HfO.sub.2) and zirconia (ZrO.sub.2), in the absence of plasma...
US-1,000,2771 Methods for chemical mechanical polishing (CMP) processing with ozone
A polymer layer on a substrate may be treated with ozone gas or with deionized water and ozone gas to increase a removal rate of the polymer layer in a chemical...
US-1,000,2769 Method for functionalizing a solid substrate, other than a substrate made of gold, via specific chemical compounds
The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical...
US-1,000,2767 Aluminum oxide landing layer for conductive channels for a three dimensional circuit device
A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a...
US-1,000,2766 High pressure low thermal budge high-k post annealing process
A method of fabricating high-k/metal gate semiconductor device by incorporating an enhanced annealing process is provided. The enhanced annealing process in...
US-1,000,2765 FinFET structure with different fin heights and method for forming the same
A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions,...
US-1,000,2764 Sputter etch material selectivity
A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the...
US-1,000,2763 Fabrication of substrates with a useful layer of monocrystalline semiconductor material
The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier...
US-1,000,2762 Multi-angled deposition and masking for custom spacer trim and selected spacer removal
Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at...
US-1,000,2761 Method for forming a multiple layer epitaxial layer on a wafer
A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The...
US-1,000,2760 Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict...
US-1,000,2759 Method of forming structures with V shaped bottom on silicon substrate
The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes applying a passivating agent containing...
US-1,000,2757 Selectively lateral growth of silicon oxide thin film
Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the...
US-1,000,2756 Fin-FET device and fabrication method thereof
A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate with a bottom portion of the sidewall surfaces...
US-1,000,2755 Process for deposition of titanium oxynitride for use in integrated circuit fabrication
A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication,...
US-1,000,2754 Substrate processing method and recording medium
Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a...
US-1,000,2753 Chamfering apparatus and method for manufacturing notchless wafer
A chamfering apparatus including chamfering part for removing notch, cleaning part for cleaning and drying wafer, and chamfered-shape measuring part for...
US-1,000,2752 Systems and methods for determining the suitability of RF sources in ultraviolet systems
A UV system for irradiating a substrate includes a RF source capable of generating RF energy, a UV lamp capable of emitting UV energy when excited by the RF...
US-1,000,2751 Ion beam irradiation apparatus
An ion beam irradiation apparatus is provided. The apparatus includes an ion source, a mass separator, and an energy filter. The mass separator sorts dopant...
US-1,000,2750 Field asymmetric ion mobility spectrometry filter
Ion filter for FAIMS fabricated using the LIGA technique. The ion filter is manufactured using a metal layer to form the ion channels and an insulating support...
US-1,000,2749 Extinguishing arcs in a plasma chamber
An arc extinguishing method for extinguishing arcs in a plasma chamber of a plasma system, comprising providing a plasma operating power during a plasma...
US-1,000,2748 Detection of grounding strap breakage
The present invention generally relates to a method for detecting the breakage of one or more grounding straps without stopping processing or opening the...
US-1,000,2747 Methods and apparatus for supplying process gas in a plasma processing system
Methods and apparatus for supplying gas in a plasma processing system that employs the single line drop approach wherein a regulator is shared among multiple...
US-1,000,2745 Plasma treatment process for in-situ chamber cleaning efficiency enhancement in plasma processing chamber
Embodiments of the disclosure include methods for in-situ chamber cleaning efficiency enhancement process for a plasma processing chamber utilized for a...
US-1,000,2744 System and method for controlling plasma density
This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. The...
US-1,000,2743 Measurement system and measurement method
For scanning electron beams and measuring overlay misalignment between an upper layer pattern and a lower layer pattern with high precision, electron beams are...
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