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Patent # Description
US-1,001,3394 System and method for re-marginating display content
A method and system for re-marginating content displayed on a display screen of a computing device when upon receiving indication of an object superposed on the...
US-1,001,3393 Parallel computer system, parallel computing method, and program storage medium
A parallel computer system including a plurality of processors configured to perform LU factorization in parallel, the system is configured to cause each of the...
US-1,001,3392 Providing access from outside a multicore processor SoC to individually configure voltages
Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an...
US-1,001,3391 Architecture emulation in a parallel processing environment
An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of...
US-1,001,3390 Secure handle for intra-and inter-processor communications
A protocol element referred to as a secure handle is described which provides an efficient and reliable method for application-to-application signaling in...
US-1,001,3389 Automatic cascaded address selection
An apparatus for addressing electronic circuits includes a host device comprising an address output, and a number of addressable electronic circuits, each...
US-1,001,3388 Dynamic peer-to-peer configuration
Provided are systems, methods, and computer-program products for enabling peer-to-peer communications between peripheral devices in a computing system. In...
US-1,001,3387 Method or apparatus for flexible firmware image management in microserver
Methods and systems are disclosed which may consolidate a flash management entity using IO virtualization. The consolidation may occur in a centralized...
US-1,001,3386 Preservation of port control block information related to logins and states of remote ports during a code load...
Information maintained in a port control block of an embedded port of a host bus adapter is stored in a host bus adapter memory, wherein the information...
US-1,001,3385 Programmable validation of transaction requests
A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge...
US-1,001,3384 Compressive sensing systems and related methods
A system to transform an input signal presented from a sensor into a spatial sequence characteristic of the signal. An input module of the system is configured...
US-1,001,3383 Method for power control handshaking of hot swappable components using programmable logic devices
A system and methodology for effectively managing, without interrupting the overall system, the power and control logic of the system during the removal,...
US-1,001,3382 Smart plug node management
In the maintenance of rack system, a computing device may implement a plurality of smart plugs and a communication bus in a system. A smart plug may be plugged...
US-1,001,3381 Media playing from a docked handheld media device
In addition to other aspects disclosed, a docking station that receives content through a wired connection from a handheld media device, plays or displays the...
US-1,001,3380 Method and system for address decoding in a data communications system using a serial data transfer bus
Embodiments of a method and system are disclosed. One embodiment of a method for address decoding in a data communications system using a serial data transfer...
US-1,001,3379 Auto-addressing of communication nodes
A system for assigning addresses to a plurality of communication nodes coupled via a power line is disclosed. Each of the plurality of communication nodes...
US-1,001,3378 ASIC chip system dedicated for optical three-dimensional sensing
The present disclosure relates to a dedicated ASIC chip system for optical three-dimensional sensing, including a DEPTH ENGINE module, a REGISTER PROCESSOR...
US-1,001,3377 PCI express fabric routing for a fully-connected mesh topology
A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is...
US-1,001,3376 System including interface circuit for driving data transmission line to termination voltage
A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line...
US-1,001,3375 System-on-chip including asynchronous interface and driving method thereof
A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and...
US-1,001,3374 Bidirectional communication method between a master terminal and a slave terminal on a single transmission line
A bidirectional communication method between a master terminal and a slave terminal on a single transmission line includes the master terminal transmitting an...
US-1,001,3373 Multi-level message passing descriptor
In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller...
US-1,001,3372 Input/output apparatus and method
An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a...
US-1,001,3371 Configurable memory circuit system and method
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a...
US-1,001,3370 Method and system for providing access of a storage system using a shared storage module as a transport mechanism
According to one embodiment, a first control module (CM) of a storage system receives a first request from a client device to read first data stored in a second...
US-1,001,3369 Server system with BMC having hard disk drive monitoring function
A server system is disclosed. The server system comprises a host system, at least one hard disk (HD) drive, a host bus adapter (HBA), at least one indicator, a...
US-1,001,3368 Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
US-1,001,3367 I/O processing system including dynamic missing interrupt and input/output detection
An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing...
US-1,001,3366 Standardized hot-pluggable transceiving unit and method for controlling the unit through a web server function
The present disclosure relates to a standardized hot-pluggable transceiving unit executing a web server function for controlling the transceiving unit, and a...
US-1,001,3365 Method for programming a control unit of a motor vehicle
A method for programming a control unit of a motor vehicle, a previous program code executed in the control unit being stored in a memory area, a new program...
US-1,001,3364 Securing data using per tenant encryption keys
One embodiment is directed to a technique which secures data on a set of storage drives of a data storage system. The technique involves encrypting data from a...
US-1,001,3363 Encryption using entropy-based key derivation
A system may encrypt the contents of a memory using an encryption key that is generated based on an entropy-based key derivation function. The system may...
US-1,001,3362 Deterministic multifactor cache replacement
Some embodiments modify caching server operation to evict cached content based on a deterministic and multifactor modeling of the cached content. The modeling...
US-1,001,3361 Method to increase performance of non-contiguously written sectors
A method of managing data in a cache upon a cache write operation includes determining a number of non-contiguously written sectors on a track in the cache and...
US-1,001,3360 Managing reuse information with multiple translation stages
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least...
US-1,001,3359 Redundant disk array storage system and method using heterogeneous disks and a lookup table
A redundant disk array method includes allocating identically sized logical blocks of storage units together to form a stripe on each of several data storage...
US-1,001,3358 Computer system and memory allocation management method
A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource...
US-1,001,3357 Managing memory access requests with prefetch for streams
Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks...
US-1,001,3356 Facilitating prefetching for data streams with multiple strides
The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor...
US-1,001,3355 Cache management in a stream computing environment that uses a set of many-core hardware processors
Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by...
US-1,001,3354 Apparatus, system, and method for atomic storage operations
A storage layer (SL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata...
US-1,001,3353 Adaptive optimization of second level cache
Adaptive optimization of second level cache is disclosed. In an example embodiment, a system includes a database server and an enterprise application server,...
US-1,001,3352 Partner-aware virtual microsectoring for sectored cache architectures
Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at...
US-1,001,3351 Transactional execution processor having a co-processor accelerator, both sharing a higher level cache
A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding...
US-1,001,3350 Data storage device and operating method thereof
A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the...
US-1,001,3349 Memory controller, method thereof, and electronic devices having the memory controller
A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group...
US-1,001,3348 Parallel memory allocator employing liveness metrics
A liveness-based memory allocation module operating so that a program thread invoking the memory allocation module is provided with an allocation of memory...
US-1,001,3347 Non-blocking parallel memory mechanisms
A transaction descriptor associated with a vertical chain of row versions is received. The vertical chain of row versions is traversed. The vertical chain is...
US-1,001,3346 Method of decreasing write amplification of NAND flash using a journal approach
A journaling approach is used to distribute data of different sizes between areas of a segment's log on a physical NAND flash erase block. The Main area...
US-1,001,3345 Storage module and method for scheduling memory operations for peak-power management and balancing
A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains...
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