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Patent # Description
US-1,002,6855 Process for making powder alloys containing cadmium and selenium
A process for preparing alloy products powders is described using a self-sustaining or self-propagating SHS-type combustion process. Binary, ternary and...
US-1,002,6854 Aluminum-based compositions and solar cells including aluminum-based compositions
The present invention describes an aluminum-based paste composition including an aluminum powder, one or more glass fits, an organo-aluminate compound; and an...
US-1,002,6853 Solar cell
A semiconductor substrate of any one of a first conductivity type and a second conductivity type includes a first main surface and a second main surface. A...
US-1,002,6852 Silicon photonics integration method and structure
Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector;...
US-1,002,6851 MPS diode
There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are...
US-1,002,6850 Transistor and fabrication method thereof
A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the...
US-1,002,6849 Structure and process for overturned thin film device with self-aligned gate and S/D contacts
Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally...
US-1,002,6848 Semiconductor device
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output...
US-1,002,6847 Semiconductor element, method for manufacturing semiconductor element, and semiconductor device including...
In a semiconductor element including an oxide semiconductor film as an active layer, stable electrical characteristics are achieved. A semiconductor element...
US-1,002,6846 Display substrate and fabrication method thereof and display device
A display substrate and a fabrication method thereof and a display device. The display substrate includes: a plurality of pixels disposed on a lower substrate;...
US-1,002,6845 Deep gate-all-around semiconductor device having germanium or group III-V active layer
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes...
US-1,002,6844 Electronic device and method for fabricating the same
Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region;...
US-1,002,6843 Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region...
A method for manufacturing an active region of a semiconductor device includes forming an implanted region in a substrate. The implanted region is adjacent to a...
US-1,002,6842 Method for producing semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first...
US-1,002,6841 Semiconductor device and manufacturing method therefor
The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the...
US-1,002,6840 Structure of semiconductor device with source/drain structures
Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a...
US-1,002,6839 Epitaxial source/drain differential spacers
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over...
US-1,002,6838 Fin-type field effect transistor and manufacturing method thereof
A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least...
US-1,002,6837 Embedded SiGe process for multi-threshold PMOS transistors
An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS...
US-1,002,6836 Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...
US-1,002,6835 Field boosted metal-oxide-semiconductor field effect transistor
A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa...
US-1,002,6834 Method of manufacturing enhanced device and enhanced device
A method of manufacturing an enhanced device and an enhance device are provided. The method comprises: preparing a substrate, and forming a non-planar structure...
US-1,002,6833 Semiconductor device and semiconductor device manufacturing method
To provide a semiconductor device with a high degree of flatness, provided is a semiconductor device including a semiconductor substrate; an element insulating...
US-1,002,6832 Power semiconductor device
A semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge...
US-1,002,6831 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front...
US-1,002,6830 Tunneling field effect transistor (TFET) having a semiconductor fin structure
A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source...
US-1,002,6829 Semiconductor device with isolated body portion
Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a...
US-1,002,6828 Method to improve GE channel interfacial layer quality for CMOS FINFET
A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium...
US-1,002,6827 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the...
US-1,002,6826 Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and...
A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The...
US-1,002,6825 Semiconductor device and method for fabricating the same
A semiconductor may include a semiconductor substrate including a first region and a second region disposed at opposite sides of the first region, a first...
US-1,002,6824 Air-gap gate sidewall spacer and method
Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall...
US-1,002,6823 Schottky contact structure for semiconductor devices and method for forming such schottky contact structure
A Schottky contact structure for a semiconductor device having a Schottky contact and an electrode for the contact structure disposed on the contact. The...
US-1,002,6822 Fabrication of nanoscale vacuum grid and electrode structure with high aspect ratio dielectric spacers between...
Some embodiments of vacuum electronics call for a grid that is fabricated in close proximity to an electrode, where, for example, the grid and electrode are...
US-1,002,6821 All-around gate field-effect transistor
An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with...
US-1,002,6820 Split gate device with doped region and method therefor
A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first...
US-1,002,6819 High voltage semiconductor devices including main conductive pattern, auxiliary conductive pattern, and spacer...
The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active...
US-1,002,6818 Field effect transistor structure with recessed interlayer dielectric and method
Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a...
US-1,002,6817 Low-stress low-hydrogen LPCVD silicon nitride
A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000...
US-1,002,6816 Semiconductor wafer and manufacturing method
A semiconductor wafer includes first and second main surfaces opposite to each other along a vertical direction, and a side surface encircling the semiconductor...
US-1,002,6815 Ultrashallow emitter formation using ALD and high temperature short time annealing
An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 110.sup.20 atoms/cm.sup.3, and...
US-1,002,6814 P-doping of group-III-nitride buffer layer structure on a heterosubstrate
An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management...
US-1,002,6813 SiC semiconductor device having a high mobility and a high threshold voltage, inverter circuit, and vehicle
A semiconductor device including a p-type SiC layer, a gate electrode, and a gate insulating layer therebetween, the gate insulating layer including a first...
US-1,002,6812 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes preparing a layer, including columns, the columns extend a first direction parallel to the surface of...
US-1,002,6811 Integrated circuit structure and method with solid phase diffusion
A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin...
US-1,002,6810 Co-integration of silicon and silicon-germanium channels for nanosheet devices
Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel...
US-1,002,6809 Semiconductor device
Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active...
US-1,002,6808 Semiconductor device including insulating film that includes negatively charged microcrystal
A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an...
US-1,002,6807 Semiconductor device and method of manufacturing semiconductor device
To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the...
US-1,002,6806 Semiconductor device including an LDMOS transistor and a RESURF structure
In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk...
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