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Patent # Description
US-1,002,6755 Array substrate and display device
An array substrate and a display device, which relates to the field of display technology. The array substrate comprises a base substrate, a plurality of first...
US-1,002,6754 Display device
The object of the present invention is to make it possible to form an LIPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a...
US-1,002,6753 Method for compensating for temperature effects in semiconductor device structures using a diode structure and...
A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A...
US-1,002,6752 Stacked SOI lateral bipolar transistor RF power amplifier and driver
An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral...
US-1,002,6751 Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing...
A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing...
US-1,002,6750 Memory device and method for operating the same
A memory device includes a peripheral circuit portion and an array portion disposed on the peripheral circuit portion. The array portion includes a bottom...
US-1,002,6749 Semiconductor memory devices having separation structures
A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend...
US-1,002,6748 Stacked type semiconductor memory device and method for manufacturing same
According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second...
US-1,002,6747 Non-volatile memory device with first gate structure in memory cell region and second gate structure in...
A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first...
US-1,002,6746 Memory devices using etching stop layers
A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a...
US-1,002,6745 Semiconductor memory cell structure
A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the...
US-1,002,6744 Method of manufacturing semiconductor device
An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of...
US-1,002,6743 Semiconductor memory device and method for manufacturing same
A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell...
US-1,002,6742 Nonvolatile memory devices having single-layered gates
A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending...
US-1,002,6741 Logic-compatible memory cell manufacturing method and structure thereof
The present disclosure presents a method of manufacturing a semiconductor structure, in which a memory cell is formed on a semiconductor substrate, the memory...
US-1,002,6740 DRAM structure with a single diffusion break
One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation...
US-1,002,6739 Semiconductor device having pillar-shaped semiconductor layers
A semiconductor device includes a first pillar-shaped semiconductor layer in which a second first-conductivity-type semiconductor layer, a first body region, a...
US-1,002,6738 Semiconductor device and semiconductor integrated circuit using the same
A semiconductor device includes a channel region of a first conductivity type, a gate insulating film formed on the channel region, a gate electrode formed on...
US-1,002,6737 Semiconductor device and manufacturing method thereof
In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate...
US-1,002,6736 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure,...
US-1,002,6735 Decoupling capacitor with metal programmable knee frequency
A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled...
US-1,002,6734 MOS device assembly
A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are...
US-1,002,6733 Complementary SOI lateral bipolar transistors with backplate bias
A method for fabricating a complementary bipolar junction transistor (BJT) integrated structure. The method includes forming a first backplate in a monolithic...
US-1,002,6732 Bidirectional power semiconductor
A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the...
US-1,002,6731 Compound semiconductor transistor integration with high density capacitor
A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound...
US-1,002,6730 Single mask level including a resistor and a through-gate implant
A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a...
US-1,002,6729 Surge-protection circuit and surge-protection method
A surge-protection circuit for a chip is provided. The surge-protection circuit includes a detection element and a protection element. The detection element is...
US-1,002,6728 Semiconductor device having biasing structure for self-isolating buried layer and method therefor
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major...
US-1,002,6727 FinFET-based ESD devices and methods for forming the same
A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of...
US-1,002,6726 Dummy gate technology to avoid shorting circuit
Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often...
US-1,002,6725 System for designing a semiconductor device, device made, and method of using the system
A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the...
US-1,002,6724 Semiconductor package and method of manufacturing the same
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least...
US-1,002,6723 Photonic integrated circuit package
Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including a lumped active...
US-1,002,6722 Light emitting component and display device
A light emitting component includes an epitaxial structure, a first electrode and a second electrode. The epitaxial structure includes a first type...
US-1,002,6721 Electronic devices with soft input-output components
An electronic device may have control circuitry coupled to input-output devices such as a display. A flexible input-output device may be formed from an...
US-1,002,6720 Semiconductor structure and a method of making thereof
An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one...
US-1,002,6719 Electronic assemblies including electronic devices mounted on non-planar subrates
The electronic assemblies described in this specification are characterized by a non-planar low-temperature co-fired ceramic substrate on which an electronic...
US-1,002,6718 Light emitting device
A light emitting device includes a first light emitting element, a second light emitting element, a substrate, and a light reflective covering member. A first...
US-1,002,6717 Multiple bond via arrays of different wire heights on a same substrate
Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires ("first wires") extend from a surface of the substrate....
US-1,002,6716 3DIC formation with dies bonded to formed RDLs
A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level...
US-1,002,6715 Semiconductor device and manufacturing method thereof
A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is...
US-1,002,6714 Integrated circuit device
Aspects of the invention relate to an integrated circuit device and method of production thereof. The integrated circuit device comprises at least one...
US-1,002,6712 ESD protection circuit with stacked ESD cells having parallel active shunt
An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first...
US-1,002,6711 Adhesive bonding composition and wafer-to-wafer bonded assembly prepared from the same
A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a...
US-1,002,6710 Electronic arrangement
An electronic arrangement comprising: a carrier; at least one connecting area on the carrier; at least one electronic component, which is fixed at least on the...
US-1,002,6709 Anisotropic electrically conductive film
An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically...
US-1,002,6708 Strong, heat stable junction
Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is...
US-1,002,6707 Wafer level package and method
A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the...
US-1,002,6706 Adding cap to copper passivation flow for electroless plating
An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated...
US-1,002,6704 Semiconductor package and method of forming the same
An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer,...
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