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Patent # Description
US-1,002,6690 Fuse blowing method and fuse blowing system
A fuse blowing method is disclosed. The fuse blowing method includes the following operations: receiving a number signal, in which the number signal includes a...
US-1,002,6689 Semiconductor device
A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed...
US-1,002,6688 Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the...
US-1,002,6687 Metal interconnects for super (skip) via integration
The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods...
US-1,002,6686 Decoupling capacitors and arrangements
Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly...
US-1,002,6685 Metal-oxide-metal (MOM) capacitor with reduced magnetic coupling to neighboring circuit and high series...
Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric...
US-1,002,6684 IC package
An IC package having a semiconductor body that includes a monolithically integrated circuit and at least two metallic contact surfaces. The integrated circuit...
US-1,002,6683 Integrated circuit package substrate
The present invention relates to an integrated circuit package substrate and, more specifically, to an integrated circuit package substrate, which exhibits...
US-1,002,6682 Ground via clustering for crosstalk mitigation
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
US-1,002,6681 Fan-out semiconductor package
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant...
US-1,002,6680 Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
US-1,002,6679 Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device
A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a...
US-1,002,6678 Fan-out semiconductor package
A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection...
US-1,002,6677 Semiconductor device
A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The...
US-1,002,6676 Semiconductor lead frame package and LED package
The present invention relates to a semiconductor lead frame package and LED package. The semiconductor lead frame package includes a die pad, a lead, a die and...
US-1,002,6675 Method of manufacture for a semiconductor device
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal...
US-1,002,6674 Cooling structure for integrated circuits and methods for forming such structure
A method for forming a cooling structure having a plurality of cooling members. The method includes: providing a template having a plurality of features, such...
US-1,002,6673 Semiconductor device and power module
A semiconductor device of a double-side cooling structure having a bus bar electrically connected, and coolers independently arranged on both sides of the...
US-1,002,6672 Recursive metal embedded chip assembly
A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device...
US-1,002,6671 Substrate design for semiconductor packages and method of forming same
An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs...
US-1,002,6670 Power module
A power module includes: a relay substrate including a first conductor layer provided on a front surface and a second conductor layer provided on a back...
US-1,002,6669 Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
US-1,002,6668 Passivation layer having an opening for under bump metallurgy
A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the...
US-1,002,6667 Method of manufacturing light-emitting device
A method of manufacturing a light-emitting device that includes a circuit board with p- and n-electrodes formed on a surface of a substrate and a light-emitting...
US-1,002,6666 Stacked die package with aligned active and passive through-silicon vias
Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in...
US-1,002,6665 Semiconductor device
For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic...
US-1,002,6664 Apparatus and method to monitor die edge defects
Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a...
US-1,002,6663 Semiconductor wafer and semiconductor device manufacturing method
A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced...
US-1,002,6662 Semiconductor structure and fabricating method thereof
A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have...
US-1,002,6661 Semiconductor device for testing large number of devices and composing method and test method thereof
Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of...
US-1,002,6660 Method of etching the back of a wafer to expose TSVs
A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device,...
US-1,002,6659 Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices
One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing...
US-1,002,6658 Methods for fabricating vertical-gate-all-around transistor structures
Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first...
US-1,002,6657 Method for producing on the same transistors substrate having different characteristics
A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one...
US-1,002,6656 Metal gate features of semiconductor die
A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and...
US-1,002,6655 Dual liner CMOS integration methods for FinFET devices
An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device...
US-1,002,6654 CMOS device with decreased leakage current and method making same
A method for making a CMOS device includes: providing a substrate with a semiconductor layer and a photoresist layer; irradiating the photoresist layer through...
US-1,002,6653 Variable gate lengths for vertical transistors
The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the...
US-1,002,6652 Horizontal nanosheet FETs and method of manufacturing the same
Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet...
US-1,002,6651 Singulation of ion-exchanged substrates
A method of making a substrate involves patterning the substrate into active areas and dicing lanes. After the substrate is patterned one or more stress layers...
US-1,002,6650 Resin composition, resin film, semiconductor device and method of manufacture thereof
A film-forming resin composition for use in encapsulating large-diameter thin-film wafers includes (A) a silicone resin having a weight-average molecular weight...
US-1,002,6649 Decoupled via fill
Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of...
US-1,002,6648 FDSOI with on-chip physically unclonable function
An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the...
US-1,002,6647 Multi-metal fill with self-align patterning
The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap...
US-1,002,6646 Packages with through-vias having tapered ends
A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material,...
US-1,002,6645 Multiple patterning process for forming pillar mask elements
A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask...
US-1,002,6644 Fabricating method of non-volatile memory device
Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate,...
US-1,002,6643 Methods of forming nanofluidic channels
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,002,6642 Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
US-1,002,6641 Isolation structure of semiconductor device
The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device...
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