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Patent # Description
US-1,002,6651 Singulation of ion-exchanged substrates
A method of making a substrate involves patterning the substrate into active areas and dicing lanes. After the substrate is patterned one or more stress layers...
US-1,002,6650 Resin composition, resin film, semiconductor device and method of manufacture thereof
A film-forming resin composition for use in encapsulating large-diameter thin-film wafers includes (A) a silicone resin having a weight-average molecular weight...
US-1,002,6649 Decoupled via fill
Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of...
US-1,002,6648 FDSOI with on-chip physically unclonable function
An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the...
US-1,002,6647 Multi-metal fill with self-align patterning
The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap...
US-1,002,6646 Packages with through-vias having tapered ends
A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material,...
US-1,002,6645 Multiple patterning process for forming pillar mask elements
A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask...
US-1,002,6644 Fabricating method of non-volatile memory device
Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate,...
US-1,002,6643 Methods of forming nanofluidic channels
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,002,6642 Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
US-1,002,6641 Isolation structure of semiconductor device
The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device...
US-1,002,6640 Structure and method for enhancing robustness of ESD device
A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure...
US-1,002,6639 Semiconductor wafer conveying tool
The semiconductor wafer conveying tool which can realize the uniform heating to a surface of a semiconductor wafer when heating the semiconductor wafer is a...
US-1,002,6638 Plasma distribution control
A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process...
US-1,002,6637 Polyimide resin, resin composition using same, and laminated film
A polyimide resin includes an acid anhydride residue; and a diamine residue, the polyimide resin including a residue of a polysiloxane diamine represented by...
US-1,002,6636 Electrostatic chuck having reduced power loss
Embodiments of the invention generally relate to an electrostatic chuck having reduced power loss, and methods and apparatus for reducing power loss in an...
US-1,002,6635 Packaging apparatus and packaging device
The present invention discloses a packaging apparatus and a packaging device. The packaging apparatus comprises a mask plate and a control circuit that is...
US-1,002,6634 Electrostatic chuck and base member for use in the same
An electrostatic chuck includes a base member and an electrostatic chuck substrate. The base member includes a cooling path. The electrostatic chuck substrate...
US-1,002,6633 Wafer boat and manufacturing method of the same
A wafer boat supporting a silicon wafer to be processed provides a sufficient anchor effect between a deposit film and a SiC coating film formed on a base...
US-1,002,6632 Wafer processing system and wafer processing method using same
A system for processing a wafer may use a wafer identification (ID) assigned by a wafer manufacturing company as an ID code of the wafer in managing the wafer...
US-1,002,6631 Plasma processing apparatus and heater temperature control method
A plasma processing apparatus is provided that converts a gas into plasma using a high frequency power and performs a plasma process on a workpiece using an...
US-1,002,6630 Retention and insulation features for lamp
Embodiments of the present disclosure generally relate to an improved retention and insulation features for lamps used as a source of heat radiation in a...
US-1,002,6629 Substrate liquid processing apparatus, substrate liquid processing method, and computer-readable storage medium...
Disclosed is a substrate liquid processing apparatus. The apparatus includes: a pure water supply unit (a rinse liquid supply unit) configured to supply pure...
US-1,002,6628 Semiconductor substrate cleaning method and cleaning system
The present invention relates to a method and a system for cleaning a semiconductor substrate wherein Al is at last partially exposed on a silicon substrate and...
US-1,002,6627 Substrate processing apparatus
A substrate processing apparatus includes a chamber, a substrate holding part, a substrate rotating mechanism, and a processing liquid supply part. The chamber...
US-1,002,6626 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,002,6625 Device comprising an encapsulation unit
A device that includes a component and an encapsulation arrangement for the encapsulation of the component with respect to moisture and/or oxygen, wherein the...
US-1,002,6624 Conductor composition ink, laminated wiring member, semiconductor element and electronic device, and method for...
A conductor of the invention is in a form of a conductive convex portion in a laminated wiring member and includes a conductive material and a liquid repellent,...
US-1,002,6623 Thin film transistor substrate, display panel, and laser annealing method
A thin film transistor substrate includes a plurality of thin film transistors arranged in columns and rows respectively on a substrate. Each of the thin film...
US-1,002,6622 Method for manufacturing semiconductor device
According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method...
US-1,002,6621 SiN spacer profile patterning
Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon nitride surface on a...
US-1,002,6620 Method of irradiating ultraviolet light on silicon substrate surface for improving quality of native oxide...
The present invention relates to the growth of a native oxide layer on a surface of a silicon substrate. Deep ultraviolet (UV) light is irradiated to thereby...
US-1,002,6619 Plasma treatment method
The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A plasma treatment method of the substrate...
US-1,002,6618 Method for improving quality of spalled material layers
Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture...
US-1,002,6617 Method and system for applying materials on a substrate
Embodiments of the invention are directed to a method of printing lines. A method may include positioning a plurality of print units according to a predefined...
US-1,002,6616 Method of reducing stress in metal film and metal film forming method
There is provided a method of reducing stress in a metal film that is highly stressed, the method including: processing the metal film by supplying a metal...
US-1,002,6615 Fin patterns with varying spacing without Fin cut
Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A...
US-1,002,6614 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region,...
US-1,002,6613 Utilization of angled trench for effective aspect ratio trapping of defects in strain-relaxed heteroepitaxy of...
Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with...
US-1,002,6612 Method for producing group III nitride crystal, group III nitride crystal, semiconductor device and apparatus...
The present invention is intended to provide a method of producing a Group III nitride crystal that prevents a halogen-containing by-product from adversely...
US-1,002,6611 Semiconductor devices
A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a...
US-1,002,6610 Silicon carbide semiconductor device manufacturing method
Provided is a method of manufacturing a silicon carbide semiconductor device with a long carrier lifetime without carrying out an additional step after a SiC...
US-1,002,6609 Nanoshape patterning techniques that allow high-speed and low-cost fabrication of nanoshape structures
A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a...
US-1,002,6608 Array substrate, method for manufacturing the same, and display device
A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and...
US-1,002,6607 Substrate processing apparatus for forming film including at least two different elements
Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by...
US-1,002,6606 Method for depositing a silicon nitride film
A method for depositing a silicon nitride film is provided. A nitrided adsorption site is formed in a recess formed in a surface of a substrate by supplying an...
US-1,002,6605 Method of reducing residual contamination in singulated semiconductor die
In one embodiment, semiconductor die are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines...
US-1,002,6604 Semiconductor cleaner systems and methods
In an embodiment, the present invention discloses a EUV cleaner system and process for cleaning a EUV carrier. The euv cleaner system comprises separate dirty...
US-1,002,6603 Manufacturing process of wafer thinning
A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of...
US-1,002,6602 Systems and methods for multipole operation
A method for identifying components of a sample includes providing a sample to an ion source and generating a plurality of ions from constituent components of...
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