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Patent # Description
US-1,002,6501 Data storage device and operating method thereof
A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all...
US-1,002,6500 Address translation stimuli generation for post-silicon functional validation
A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory...
US-1,002,6499 Memory testing system
Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The...
US-1,002,6498 Simultaneous scan chain initialization with disparate latches
Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data...
US-1,002,6497 Charge injection noise reduction in sample-and-hold circuit
A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a...
US-1,002,6496 Shift register unit and method for driving the same, gate drive circuit and display device
A shift register unit and a method for driving the shift register unit, a gate drive circuit and a display device are provided. The shift register unit includes...
US-1,002,6495 Method of controlling magnetization state using imprinting technique
A method of controlling a magnetization state using an imprinting technique may be provided. The method may include moving first and second magnetic structures,...
US-1,002,6494 Word line voltage generator for calculating optimum word line voltage level for programmable memory array
A method of generating a high differential read current through a non-volatile memory, includes receiving a voltage read input from a word line voltage...
US-1,002,6493 PPA (power performance area) efficient architecture for rom (read only memory) and a ROM bitcell without a...
Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address...
US-1,002,6492 Multi-die programming with die-jumping induced periodic delays
Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more...
US-1,002,6491 Semiconductor memory device and memory system
A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and...
US-1,002,6490 Programming method for reducing a width of a threshold voltage distribution curve of memory cells
A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping...
US-1,002,6489 Semiconductor memory device and operating method thereof
The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor...
US-1,002,6488 Non-volatile memory with read disturb detection for open blocks
A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block...
US-1,002,6487 Non-volatile memory with customized control of injection type of disturb during program verify for improved...
A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the...
US-1,002,6486 First read countermeasures in memory
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on...
US-1,002,6485 Semiconductor device
A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO...
US-1,002,6484 High-speed readable semiconductor storage device
According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a...
US-1,002,6483 Program temperature aware data scrub
Techniques disclosed herein cope with cross-temperature effects in non-volatile memory systems. One technology disclosed herein includes an apparatus and method...
US-1,002,6482 Semiconductor memory device, erasing method and programing method thereof
A semiconductor memory device, an erasing method and a programming method are provided. The semiconductor memory device includes a memory array, which includes...
US-1,002,6481 Semiconductor device
A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with...
US-1,002,6480 Memory device including multiple select gates and different bias conditions
Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string...
US-1,002,6479 Content addressable memory device having electrically floating body transistor
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the...
US-1,002,6478 Biasing scheme for multi-layer cross-point ReRAM
Systems and methods for improving the performance of a non-volatile memory array during a memory operation by concurrently applying two different selected word...
US-1,002,6477 Selector relaxation time reduction
In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first...
US-1,002,6476 Bi-polar memristor
A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of...
US-1,002,6475 Adaptive configuration of non-volatile memory
Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values...
US-1,002,6474 Switched memristor analog tuning
Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched...
US-1,002,6473 Non-volatile memory device for selectively performing recovery operation and method of operating the same
A non-volatile memory device for selectively performing a recovery operation and a method of operating the same are provided. The method of operating a...
US-1,002,6472 Multi-port memory and semiconductor device
In a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a...
US-1,002,6471 System-on-chip and electronic device having the same
A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device,...
US-1,002,6470 SRAM arrays and methods of manufacturing same
An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of...
US-1,002,6469 Semiconductor device performing write operation and write leveling operation
A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second...
US-1,002,6468 DRAM with segmented word line switching circuit for causing selection of portion of rows and circuitry for a...
This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a...
US-1,002,6467 High-bandwidth memory application with controlled impedance loading
A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and...
US-1,002,6466 Staggered exit from memory power-down
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing...
US-1,002,6465 Nonvolatile memory
According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a...
US-1,002,6464 Devices, systems, and methods for increasing the usable life of a storage system by optimizing the energy of...
In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and...
US-1,002,6463 Semiconductor device and method of operation
A semiconductor device includes a clock shifting circuit suitable for shifting a write pulse which is synchronized with a clock, in response to write latency...
US-1,002,6462 Apparatuses and methods for providing constant DQS-DQ delay in a memory device
Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line...
US-1,002,6461 Semiconductor devices and semiconductor systems including the same
A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a...
US-1,002,6460 Techniques to mitigate bias drift for a memory device
Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is...
US-1,002,6459 Data gathering in memory
Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of...
US-1,002,6458 Memories and methods for performing vector atomic memory operations with mask control and variable data length...
Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder....
US-1,002,6457 Device having multiple channels with calibration circuit shared by multiple channels
An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second...
US-1,002,6456 Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor...
Write-assist circuits for memory bit cells ("bit cells") employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and...
US-1,002,6455 System and method for controlling environmental conditions within an automated data storage library
A system and method for controlling at least one environmental condition within at least one data storage library. The system may include at least one data...
US-1,002,6454 Storage system with cross flow cooling of power supply unit
Apparatus and method for cooling a power supply unit in a storage system. In some embodiments, a storage system includes a first section for receiving a...
US-1,002,6453 Hard disk tray and hard disk rack assembly
A hard disk tray adapted for accommodating a hard disk having a plurality of screw holes at two sides is provided. The hard disk tray includes a body and a...
US-1,002,6452 Method and apparatus for generating 3D audio positioning using dynamically optimized audio 3D space perception cues
An apparatus generating audio cues for content indicative of the position of audio objects within the content comprising: an audio processor receiving raw audio...
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