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Patent # Description
US-1,002,5733 Data output dispatching device and method
The present invention discloses a data output dispatching device and method capable of reducing the probability of packets from the same queue being transmitted...
US-1,002,5732 Preserving deterministic early valid across a clock domain crossing
A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal...
US-1,002,5731 Memory module and circuit providing load isolation and noise reduction
Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively...
US-1,002,5730 Register device and method for software programming
A communication device is provided. The communication device includes a master interface unit that is configured to provide an interface between a processor and...
US-1,002,5729 Memory lock system with manipulatable input device and method of operation thereof
An electronic memory system and method of operation thereof includes: a manipulatable lock for receiving an input; a controller for enabling a communication...
US-1,002,5728 Flash memory device for storing sensitive information and other data
A flash memory process and device for encrypting and storing data in a non-volatile flash memory associated with a host system. The device includes a flash...
US-1,002,5727 Relay mechanism to facilitate processor communication with inaccessible input/output (I/O) device
A method includes transmitting, by a first processing device, a signal to a second relay processing device. The signal includes a message for the second relay...
US-1,002,5726 Method in a memory management unit for managing address translations in two stages
A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address...
US-1,002,5725 Dynamic address translation table allocation
A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the...
US-1,002,5724 Address mapping method of memory system
Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a...
US-1,002,5723 Multiple page-size translation lookaside buffer
An example method includes receiving a request to change a page size managed by a translation lookaside buffer (TLB), wherein the TLB is currently managing a...
US-1,002,5722 Efficient translation reloads for page faults with host accelerator directly accessing process address space...
Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a...
US-1,002,5721 Input/output memory map unit and northbridge
The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also...
US-1,002,5720 Cache organization and method
A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata,...
US-1,002,5719 Cache memory system and processor system
A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an...
US-1,002,5718 Modifying provisioned throughput capacity for data stores according to cache performance
Modifications to throughput capacity provisioned at a data store for servicing access requests to the data store may be performed according to cache performance...
US-1,002,5717 Multi-dimensional prefetching
An apparatus comprises an event memory to store one or more events, and a prefetch circuit. The prefetch circuit a) detects a current stride between a first...
US-1,002,5716 Mapping processor address ranges to persistent storage
A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an...
US-1,002,5715 Conditional inclusion of data in a transactional memory read set
Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A...
US-1,002,5714 Memory type range register with write-back cache strategy for NVDIMM memory locations
A computer system includes a dual in-line memory module (DIMM), such as a registered DIMM (RDIMM), and a non-volatile DIMM (NVDIMM). A central processing unit...
US-1,002,5713 System and method for removing data from processor caches in a distributed multi-processor computer system
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor...
US-1,002,5712 Power-safe data management system
Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In...
US-1,002,5711 Hybrid write-through/write-back cache policy managers, and related systems and methods
Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write...
US-1,002,5710 Pattern for integrating primary and secondary data stores in a sharded data domain
Example systems and methods for integrating a sharded primary data store (e.g., a source-of-truth relational database management system), a secondary data store...
US-1,002,5709 Convolutional de-interleaver and convolutional de-interleaving method
A convolutional de-interleaver for processing multiple groups of convolutional interleaved data is provided. The groups of convolutional interleaved data...
US-1,002,5708 Memory management method, memory control circuit unit and memory storage apparatus
A memory management method, and a memory control circuit unit and a memory storage apparatus using this method are provided. The method includes performing a...
US-1,002,5707 Non-volatile semiconductor memory device
A flash memory includes a memory array including a memory mat MAT-0, MAT-1; a page buffer 170-0, holding data read from the memory mat MAT-0; a page buffer...
US-1,002,5706 Control device, storage device, and storage control method
A control device includes: a management information generation unit configured to generate or update logical-physical block address management information with...
US-1,002,5705 Apparatus and system for object-based storage solid-state device
An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary...
US-1,002,5704 Memory system including PE count circuit and method of operating the same
A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area...
US-1,002,5703 Collectable display device
Provided is a collectable display device, including at least one display panel having at least one user accessible opening for housing and displaying at least...
US-1,002,5702 Browser capable of saving and restoring content item state
Features are disclosed for storing content items, such as content pages, applications, and other network-accessible content, such that changes to the state of...
US-1,002,5701 Application pre-release report
Various embodiments provide an automated testing analysis tool, termed a "pre-release analysis tool", that tests applications for functional and nonfunctional...
US-1,002,5700 Data mining technique with n-Pool evolution
Roughly described, a training database contains N segments of data samples. Candidate individuals identify a testing experience level, a fitness estimate, a...
US-1,002,5699 Method and system for reviewing of clustered-code analysis warnings
A system and method for reviewing of warning generated during static analysis of a clustered software code by identifying, common point warnings and unique...
US-1,002,5698 System and method for efficiently predicting testing schedule and stability of applications
A system and computer-implemented method for efficiently predicting software testing schedule of one or more applications is provided. The system comprises a...
US-1,002,5697 Generation of automated unit tests for a controller layer system and method
A method, computer program product, and computer system for receiving, by a computing device, a selection of one or more files for which to have one or more...
US-1,002,5696 System and method for equivalence class analysis-based automated requirements-based test case generation
A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual...
US-1,002,5695 Enhancing GUI automation testing using video
A method, computer program product, and system for testing an application on a GUI are provided. A request to perform a test of an application is received. The...
US-1,002,5694 Monitoring activity of software development kits using stack trace analysis
Method, product and system for analyzing an execution of a program which uses Software Development Kits (SDKs), wherein the program is configured to invoke...
US-1,002,5693 Pseudo hardware watch points for remote debugging of non-initialized processors
A hardware access layer (HAL) is combined with a configurable shadow mechanism, that copies the specified memory or register segments accessed in remote...
US-1,002,5692 Scalable continuous integration and delivery systems and methods
A scalable continuous integration (CI) system and/or method may be provided to manage and implement a plurality of code changes submitted in a code base. In...
US-1,002,5691 Verification of complex software code using a modularized architecture
A technique verifies a compound software code using a modularized architecture. The compound software code may be divided into smaller components or modules...
US-1,002,5690 Method of reordering condition checks
Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code...
US-1,002,5689 Enhanced policy editor with completion support and on demand validation
In an approach to providing completion support and on demand validation in a web tool that operates on live resources, one or more computer processors create...
US-1,002,5688 System and method for detecting data extrusion in software applications
Comprehensive techniques identify data leaks in software applications using Asset Flow Analysis (AFA) to determine whether critical data leaves a system through...
US-1,002,5687 Event rate change based hardware performance data collection
An approach for writing performance data to memory based on a hardware event rate change involving receiving a hardware event count associated with a computer...
US-1,002,5686 Generating and communicating platform event digests from a processor of a system
In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a...
US-1,002,5685 Impedance compensation based on detecting sensor data
A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller...
US-1,002,5684 Lending target device resources to host device computing environment
Various models may enable a first device to share a device resource with a second device in various contexts, such as sharing computing sessions via terminal...
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