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Patent # Description
US-1,003,2904 Semiconductor device with non-isolated power transistor with integrated diode protection
A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and...
US-1,003,2903 Threshold voltage adjustment of a transistor
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-1,003,2902 LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode
An LDMOS is formed with a second gate stack over n.sup.- drift region, having a common gate electrode with the gate stack, and having a higher work function...
US-1,003,2901 Semiconductor device with trench-like feed-throughs
A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through...
US-1,003,2900 Vertical DMOS transistor
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially...
US-1,003,2899 Semiconductor device and method therefor including multiple cap layers with amorphous layer
A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second...
US-1,003,2898 Method for manufacturing a HEMT transistor and HEMT transistor with improved electron mobility
A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure...
US-1,003,2897 Single electron transistor with self-aligned Coulomb blockade
Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed...
US-1,003,2896 Semiconductor device and manufacturing method thereof
The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer...
US-1,003,2895 Semiconductor device and method for manufacturing the same
A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in...
US-1,003,2894 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
After a titanium nitride film is formed to cover an interlayer insulating film, a first nickel film is formed on a front surface of a silicon carbide base...
US-1,003,2893 Bipolar transistor
A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has...
US-1,003,2892 Semiconductor device
This semiconductor device comprises an active layer that is formed of an oxide magnetic material and a porous dielectric body that contains water and is...
US-1,003,2891 FinFET based flash memory cell
A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating...
US-1,003,2890 Method of manufacturing semiconductor devices
Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and...
US-1,003,2889 Self-aligned passivation of active regions
A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species,...
US-1,003,2888 Semiconductor device, method for manufacturing semiconductor device, and electronic appliance having...
To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is...
US-1,003,2887 Method of forming a contact
A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and...
US-1,003,2886 Semiconductor device
A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with...
US-1,003,2885 Channel replacement and bimodal doping scheme for bulk finFet threshold voltage modulation with reduced...
A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material...
US-1,003,2884 Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling
Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed...
US-1,003,2883 Silicon germanium heterojunction bipolar transistor structure and method
Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially...
US-1,003,2882 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
A recombination center is formed within the bandgap of at least a silicon carbide material used to form an n.sup.- drift layer in a SiC-MOSFET. This...
US-1,003,2881 Mask, manufacturing method thereof and exposure system
A mask, including a transparent substrate and mask patterns formed on a surface of the transparent substrate, wherein the mask patterns include a first area for...
US-1,003,2880 Method for forming ohmic contacts
Implementations of an ohmic contact for a gallium nitride (GaN) device may include: a first layer including aluminum coupled directly with the GaN device; the...
US-1,003,2879 Thin film transistor substrate, display apparatus including the same, method of manufacturing the same, and...
A thin film transistor (TFT) substrate includes an insulating layer, an electrode on the insulating layer, and a main buffering layer connecting a side surface...
US-1,003,2878 Semiconductor device with a semiconductor via and laterally connected electrode
A semiconductor device includes a semiconductor body having a first surface and a second surface, at least one electrode arranged in at least one trench...
US-1,003,2877 FinFET and method of forming same
A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask...
US-1,003,2876 Contact silicide having a non-angular profile
A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is...
US-1,003,2875 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a second semiconductor layer formed over the first...
US-1,003,2874 Semiconductor device with reduced on-state resistance
A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type...
US-1,003,2873 Semiconductor device and method of forming the same
A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the...
US-1,003,2872 Semiconductor device, method for manufacturing the same, and apparatus for manufacturing semiconductor device
To manufacture a semiconductor device using an oxide semiconductor with high reliability and less variation in electrical characteristics, objects are to...
US-1,003,2871 Silicon carbide semiconductor device and method for manufacturing same
A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation...
US-1,003,2870 Low defect III-V semiconductor template on porous silicon
A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a...
US-1,003,2869 Fin field effect transistor (FinFET) device having position-dependent heat generation and method of making the same
A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major...
US-1,003,2868 High performance super-beta NPN (SBNPN)
A method for making a super .beta. NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a...
US-1,003,2867 Forming bottom isolation layer for nanosheet technology
A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet...
US-1,003,2866 Semiconductor device and method of manufacturing semiconductor device
In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge...
US-1,003,2865 Powers semiconductor device
A power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and...
US-1,003,2864 Semiconductor device having field insulation layer between two fins
Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first...
US-1,003,2863 Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral...
US-1,003,2862 Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method...
US-1,003,2861 Semiconductor device with field threshold MOSFET for high voltage termination
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and...
US-1,003,2860 Semiconductor device and fabrication method thereof
A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a...
US-1,003,2859 Methods for manufacturing integrated circuit devices having features with reduced edge curvature
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution...
US-1,003,2858 Nanosheet capacitor
A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged...
US-1,003,2857 Etchstop layers and capacitors
Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense...
US-1,003,2856 Nanosheet capacitor
A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged...
US-1,003,2855 Advanced metal insulator metal capacitor
A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region...
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