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Patent # Description
US-1,003,2754 Light-emitting apparatus and illumination apparatus
A method of manufacturing a light-emitting apparatus includes mounting a first light-emitting element and a second light-emitting element on a substrate. A...
US-1,003,2753 Flexible lighting device having both visible and infrared light-emitting diodes
A flexible lighting array, comprising: a flexible substrate; a pair of first electrical connectors formed on the flexible substrate; a pair of second electrical...
US-1,003,2752 Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for...
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face...
US-1,003,2751 Ultrathin layer for forming a capacitive interface between joined integrated circuit components
Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at...
US-1,003,2750 Integrated DC-DC power converters through face-to-face bonding
DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In...
US-1,003,2749 Three-dimensional chip-to-wafer integration
An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is...
US-1,003,2748 Semiconductor package and fabricating method thereof
A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various...
US-1,003,2747 Light emitting diode package structure and manufacturing method thereof
A light emitting diode package structure and a manufacturing method thereof are disclosed. The light emitting diode package structure includes a carrier...
US-1,003,2746 Semiconductor device having recessed edges and method of manufacture
A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric...
US-1,003,2745 Method of manufacturing semiconductor device
To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension...
US-1,003,2744 Universal surface-mount semiconductor package
A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly...
US-1,003,2743 Method for producing a semiconductor module
A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of...
US-1,003,2742 Method for obtaining a bonding surface for direct bonding
A process for obtaining a bonding surface for direct bonding includes: a) providing a substrate based on a sintered metal having a base surface with an RMS...
US-1,003,2741 Bonding wire for semiconductor device
There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a...
US-1,003,2740 Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a...
US-1,003,2739 Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper...
US-1,003,2738 Method for forming bump of semiconductor package
The present invention provides a method for forming bumps of a semiconductor package to suppress a final height difference between main bumps and support bumps...
US-1,003,2737 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding...
US-1,003,2736 Semiconductor device
A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source...
US-1,003,2735 Semiconductor structure and method of forming
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device...
US-1,003,2734 Semiconductor package system and method
A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die...
US-1,003,2733 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip...
US-1,003,2732 Semiconductor module arrangement
In a switching module structure that includes a low-impedance path to ground, such as a parasitic capacitance of an insulating substrate, a further insulating...
US-1,003,2731 Voltage compensated switch stack
A radio frequency (RF) switch arrangement that improves the voltage handling capacity of a stack of switching elements (e.g., field-effect transistors (FETs))....
US-1,003,2730 Semiconductor chip having tampering feature
Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device...
US-1,003,2729 Apparatus and method for generating identification key
Provided is an apparatus for generating an identification key by using process variation in a conductive layer manufacturing process. The apparatus may include...
US-1,003,2728 Trench MOSFET device and the preparation method thereof
A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a...
US-1,003,2727 Electrical package including bimetal lid
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads...
US-1,003,2726 Embedded vibration management system
Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by...
US-1,003,2725 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a...
US-1,003,2724 Silicon carbide semiconductor base, method of crystal axis alignment in silicon carbide semiconductor base, and...
On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark...
US-1,003,2723 Metal layer independent version identifier
Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status...
US-1,003,2722 Semiconductor package structure having am antenna pattern and manufacturing method thereof
A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The...
US-1,003,2721 Low resistance contact structures for trench structures
An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel...
US-1,003,2719 Semiconductor device structures
A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of...
US-1,003,2717 Vertical fuse structures
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
US-1,003,2716 Advanced E-fuse structure with controlled microstructure
In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode...
US-1,003,2715 Ultra high performance interposer
An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in...
US-1,003,2714 Semiconductor switch
A semiconductor switch includes an insulating film on a semiconductor substrate. A switching circuit is on a first portion of the insulating film. The switching...
US-1,003,2713 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes...
US-1,003,2712 Semiconductor structure
One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first...
US-1,003,2711 Integrating metal-insulator-metal capacitors with air gap process flow
Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect...
US-1,003,2710 Via pattern to reduce crosstalk between differential signal pairs
An integrated circuit (IC) system includes an IC coupled to a package. The package, in turn, is coupled to a ball grid array. The integrated circuit is...
US-1,003,2709 Embedding thin chips in polymer
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a...
US-1,003,2708 Circuit board and smart card module and smart card utilizing the same
A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region...
US-1,003,2707 Post-grind die backside power delivery
Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a...
US-1,003,2706 Package substrates
A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy...
US-1,003,2705 Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a...
US-1,003,2704 Reducing cracking by adjusting opening size in pop packages
A package includes a device die, a molding material molding the device die therein, and a surface dielectric layer at a surface of the package. A corner opening...
US-1,003,2703 Package-on-package semiconductor assemblies and methods of manufacturing the same
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
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