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Patent # Description
US-1,003,2702 Package structure and manufacturing method thereof
A package structure including a first redistribution circuitry and a second redistribution circuitry is provided. The first redistribution circuitry has a...
US-1,003,2700 Positional relationship among components of semiconductor device
A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively...
US-1,003,2699 Flip chip self-alignment features for substrate and leadframe applications
Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of...
US-1,003,2698 Interconnection structure with confinement layer
An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic...
US-1,003,2697 Electronic component package and electronic device including the same
An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first...
US-1,003,2696 Chip package using interposer substrate with through-silicon vias
A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies...
US-1,003,2695 Powermap optimized thermally aware 3D chip package
A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked...
US-1,003,2694 Power electronics assemblies having a semiconductor cooling chip and an integrated fluid channel system
A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to...
US-1,003,2693 Heat transfer chassis and method for forming the same
A system includes a front plate, a manifold cover, and bridge heat sinks. The manifold cover is secured to the front plate to define a fluid distribution...
US-1,003,2692 Semiconductor package structure
Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a...
US-1,003,2691 Phase changing on-chip thermal heat sink
A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the...
US-1,003,2690 Semiconductor structure including a thermally conductive, electrically insulating layer
A thermally conductive and electrically insulating layer is provided over a semiconductor structure.
US-1,003,2689 Double-side cooling type power module and producing method thereof
Disclosed herein are a double-side cooling type power module and a producing method thereof. The double-side cooling type power module includes a pair of...
US-1,003,2688 Electronic component and method for dissipating heat from a semiconductor die
In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core...
US-1,003,2687 Temperature control device, semiconductor device including the same, and method for controlling the...
A temperature control device for controlling a temperature of a semiconductor device including a first chip and a second chip. The temperature control device...
US-1,003,2686 Motor drive device and method capable of notifying malfunction in fluid flow in heat sink
A motor drive device detects the malfunction of a flow path in a heat sink based on the temperature of the device. The motor drive device includes: a...
US-1,003,2685 Electronic component and circuit module
An electronic component includes a core, a winding, and an electrode. A flange of the core includes a body having a first surface that faces a top side and is...
US-1,003,2684 Lead bonding structure
A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The...
US-1,003,2683 Time temperature monitoring system
A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region;...
US-1,003,2682 Multi-die wafer-level test and assembly without comprehensive individual die singulation
Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an...
US-1,003,2681 Etch metric sensitivity for endpoint detection
Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals...
US-1,003,2680 Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
US-1,003,2679 Self-aligned doping in source/drain regions for low contact resistance
Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method...
US-1,003,2678 Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor...
Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an...
US-1,003,2677 Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers...
US-1,003,2676 Vertical field effect transistor having U-shaped top spacer
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer...
US-1,003,2675 Method for fabricating semiconductor device
The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is...
US-1,003,2674 Middle of the line subtractive self-aligned contacts
A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching...
US-1,003,2673 Semiconductor devices and methods for manufacturing the same
A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a...
US-1,003,2672 Method of fabricating a semiconductor device having contact structures
A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of...
US-1,003,2671 Manufacturing method of semiconductor device using peeling
The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an...
US-1,003,2670 Plasma dicing of silicon carbide
A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate...
US-1,003,2669 Wafer dividing method
A wafer having on one side a device area with devices partitioned by division lines is divided into dies. An adhesive tape for protecting the devices is...
US-1,003,2668 Chamferless via structures
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric...
US-1,003,2667 Semiconductor device and manufacturing method thereof
When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and...
US-1,003,2666 Semiconductor memory device and method of fabricating the same
A semiconductor memory device is disclosed. The semiconductor memory device includes a substrate including cell and peripheral regions, a stack on the cell...
US-1,003,2665 Method of forming semiconductor device
A method for forming a semiconductor device includes the following steps. An IMD layer is provided on a substrate. A plurality of block patterns is formed on...
US-1,003,2664 Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods...
US-1,003,2663 Anneal after trench sidewall implant to reduce defects
A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench...
US-1,003,2662 Packaged semiconductor devices and packaging methods thereof
Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a packaged semiconductor device includes a first device and...
US-1,003,2661 Semiconductor device, method, and tool of manufacture
A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in...
US-1,003,2660 Porous barrier for evenly distributed purge gas in a microenvironment
An improved system and method for purging a microenvironment to desired levels of relative humidity, oxygen, or particulates through the implementation of a...
US-1,003,2659 Methods and systems for preventing unsafe operations
A system for preventing an unsafe operation of at least one machine communicatively coupled to a computing device. The system includes the computing device...
US-1,003,2658 Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for...
US-1,003,2657 Apparatus and method for treating a substrate
The present disclosure relates to an apparatus and a method for treating a substrate with a liquid. A substrate treating apparatus includes a substrate...
US-1,003,2656 Substrate processing apparatus
A substrate processing apparatus configured to rotate a substrate, such as a wafer, is disclosed. The substrate processing apparatus includes: a substrate...
US-1,003,2655 Substrate cleaning device, substrate cleaning apparatus, method for manufacturing cleaned substrate and...
A substrate cleaning device 1 includes a substrate holding unit 10 configured to hold a substrate W, a first cleaning unit 11 having a first cleaning member 11a...
US-1,003,2654 Substrate treatment apparatus
A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a...
US-1,003,2653 Mould, carrier with encapsulated electronic components, separated encapsulated electronic component and method...
The invention relates to a mold for encapsulating electronic components mounted on a carrier, with at least two mold parts which are displaceable relative to...
US-1,003,2652 Semiconductor package having improved package-on-package interconnection
The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a...
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