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Patent # Description
US-1,003,2681 Etch metric sensitivity for endpoint detection
Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals...
US-1,003,2680 Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
US-1,003,2679 Self-aligned doping in source/drain regions for low contact resistance
Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method...
US-1,003,2678 Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor...
Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an...
US-1,003,2677 Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers...
US-1,003,2676 Vertical field effect transistor having U-shaped top spacer
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer...
US-1,003,2675 Method for fabricating semiconductor device
The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is...
US-1,003,2674 Middle of the line subtractive self-aligned contacts
A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching...
US-1,003,2673 Semiconductor devices and methods for manufacturing the same
A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a...
US-1,003,2672 Method of fabricating a semiconductor device having contact structures
A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of...
US-1,003,2671 Manufacturing method of semiconductor device using peeling
The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an...
US-1,003,2670 Plasma dicing of silicon carbide
A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate...
US-1,003,2669 Wafer dividing method
A wafer having on one side a device area with devices partitioned by division lines is divided into dies. An adhesive tape for protecting the devices is...
US-1,003,2668 Chamferless via structures
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric...
US-1,003,2667 Semiconductor device and manufacturing method thereof
When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and...
US-1,003,2666 Semiconductor memory device and method of fabricating the same
A semiconductor memory device is disclosed. The semiconductor memory device includes a substrate including cell and peripheral regions, a stack on the cell...
US-1,003,2665 Method of forming semiconductor device
A method for forming a semiconductor device includes the following steps. An IMD layer is provided on a substrate. A plurality of block patterns is formed on...
US-1,003,2664 Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods...
US-1,003,2663 Anneal after trench sidewall implant to reduce defects
A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench...
US-1,003,2662 Packaged semiconductor devices and packaging methods thereof
Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a packaged semiconductor device includes a first device and...
US-1,003,2661 Semiconductor device, method, and tool of manufacture
A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in...
US-1,003,2660 Porous barrier for evenly distributed purge gas in a microenvironment
An improved system and method for purging a microenvironment to desired levels of relative humidity, oxygen, or particulates through the implementation of a...
US-1,003,2659 Methods and systems for preventing unsafe operations
A system for preventing an unsafe operation of at least one machine communicatively coupled to a computing device. The system includes the computing device...
US-1,003,2658 Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for...
US-1,003,2657 Apparatus and method for treating a substrate
The present disclosure relates to an apparatus and a method for treating a substrate with a liquid. A substrate treating apparatus includes a substrate...
US-1,003,2656 Substrate processing apparatus
A substrate processing apparatus configured to rotate a substrate, such as a wafer, is disclosed. The substrate processing apparatus includes: a substrate...
US-1,003,2655 Substrate cleaning device, substrate cleaning apparatus, method for manufacturing cleaned substrate and...
A substrate cleaning device 1 includes a substrate holding unit 10 configured to hold a substrate W, a first cleaning unit 11 having a first cleaning member 11a...
US-1,003,2654 Substrate treatment apparatus
A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a...
US-1,003,2653 Mould, carrier with encapsulated electronic components, separated encapsulated electronic component and method...
The invention relates to a mold for encapsulating electronic components mounted on a carrier, with at least two mold parts which are displaceable relative to...
US-1,003,2652 Semiconductor package having improved package-on-package interconnection
The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a...
US-1,003,2651 Package structures and method of forming the same
Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first...
US-1,003,2650 Die mounting system and die mounting method
A die mounting system in which die supply device is set on component mounter and dies supplied from die supply device are mounted on circuit board by mounting...
US-1,003,2649 Method of fabricating low-profile footed power package
A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which...
US-1,003,2648 Method of manufacturing power-module substrate with heat-sink
A maximum length of a heat sink is set as "L" and a warp amount of the heat sink is set as "Z"; the warp amount "Z" is set as a positive value if a bonded...
US-1,003,2647 Low CTE component with wire bond interconnects
A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such...
US-1,003,2646 Robust multi-layer wiring elements and assemblies with embedded microelectronic elements
An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer...
US-1,003,2645 Semiconductor package with multiple molding routing layers and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing...
US-1,003,2644 Barrier chemical mechanical planarization slurries using ceria-coated silica abrasives
Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer tunable polishing...
US-1,003,2643 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and...
Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are...
US-1,003,2642 Substrate liquid processing apparatus
Disclosed is a substrate liquid processing apparatus that includes: a liquid processing unit that performs a liquid processing on a film formed on a surface of...
US-1,003,2641 Semiconductor device and method of fabricating the same
A semiconductor device is provided as follows. A first fin-type pattern is disposed on a substrate. A first field insulating film is adjacent to a sidewall of...
US-1,003,2640 Formation of semiconductor structure with a photoresist cross link and de-cross link process
Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link...
US-1,003,2639 Methods for improved critical dimension uniformity in a semiconductor device fabrication process
Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first...
US-1,003,2638 Method of fabricating pattern structure
A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer...
US-1,003,2637 Sacrificial shorting straps for superconducting qubits
A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode...
US-1,003,2635 Thin film metal silicides and methods for formation
The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide...
US-1,003,2634 Metal gate stack having TaAlCN layer
A method includes forming a gate stack over a semiconductor substrate; forming an interlayer dielectric layer surrounding the gate stack; and at least partially...
US-1,003,2633 Image transfer using EUV lithographic structure and double patterning process
An EUV lithographic structure includes an EUV photosensitive resist layer disposed on a hardmask layer, wherein the EUV lithographic structure is free of an...
US-1,003,2632 Selective gas etching for self-aligned pattern transfer
Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical...
US-1,003,2631 Method of fabricating mask pattern
A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between...
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