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Patent # Description
US-1,003,2529 Nuclear reactor internal electric control rod drive mechanism assembly
A magnetic jack control rod drive rod drive system having the magnetic coils that operate the moving parts of the drive system wound from anodized aluminum...
US-1,003,2528 Fully ceramic micro-encapsulated (FCM) fuel for CANDUs and other reactors
A fuel pellet for a nuclear reactor includes a plurality of tristructural-isotropic fuel particles embedded in a structural silicon carbide matrix. A method of...
US-1,003,2527 Method for fabricating silicon carbide assemblies
A method for fabricating assemblies includes providing first and second components that include ceramic, metal, or composite; positioning a multiphase joining...
US-1,003,2526 Patient safety processor
A processor-based system for analyzing physiologic data and medical care is provided wherein the patient data is analyzed to construct images that are...
US-1,003,2525 Fuse circuit, repair control circuit, and semiconductor apparatus including the same
A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect...
US-1,003,2524 Techniques for determining local interconnect defects
Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run...
US-1,003,2523 Memory device including extra capacity and stacked memory device including the same
A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array,...
US-1,003,2522 Three-transistor OTP memory cell
An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming...
US-1,003,2521 PUF value generation using an anti-fuse memory array
A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation...
US-1,003,2520 Power system with detecting function
A power system with detecting function includes a power source, a power level detector, and a power floating detector. The power source includes multiple...
US-1,003,2519 Semiconductor memory device in which bit line pre-charging, which is based on result of verify operation, is...
A semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier electrically connected to the bit...
US-1,003,2517 Memory architecture having two independently controlled voltage pumps
A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first...
US-1,003,2516 Duo content addressable memory (CAM) using a single CAM
Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes...
US-1,003,2515 Memory repair system and method therefor
A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein...
US-1,003,2514 Semiconductor memory having both volatile and non-volatile functionality including resistance change material...
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein...
US-1,003,2512 Non-volatile semiconductor memory device
A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements...
US-1,003,2511 Memory with dynamic permissible bit write logic and method
For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected...
US-1,003,2510 Multimodal memristor memory
A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor...
US-1,003,2509 Semiconductor memory device including variable resistance element
According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first...
US-1,003,2508 Method and apparatus for multi-level setback read for three dimensional crosspoint memory
In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback...
US-1,003,2507 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual...
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in...
US-1,003,2506 Configurable pseudo dual port architecture for use with single port SRAM
A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock...
US-1,003,2505 Dynamic random access memory with pseudo differential sensing
Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage...
US-1,003,2504 Semiconductor memory device and operating method thereof
A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a...
US-1,003,2503 Semiconductor memory device performing refresh operation based on weak cell information stored in memory array...
A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell...
US-1,003,2502 Method for calibrating capturing read data in a read data path for a DDR memory interface circuit
A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps...
US-1,003,2501 Semiconductor device
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a...
US-1,003,2500 Memory disturb recovery scheme for cross-point memory arrays
Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh...
US-1,003,2499 Magnetic memory device including two magnetic bodies
According to one embodiment, a magnetic memory device includes a first magnetic body and a second magnetic body. The first magnetic body extends in a first...
US-1,003,2498 Memory cell unit and recurrent neural network including multiple memory cell units
A memory cell unit and a recurrent neural network including memory cell units are provided. The memory cell unit includes a first time gate configured to...
US-1,003,2497 Flexible point-to-point memory topology
An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the...
US-1,003,2496 Variable filter capacitance
Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two...
US-1,003,2495 Bitline senseamplifier and semiconductor memory apparatus using the same
A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and...
US-1,003,2494 Data processing systems and a plurality of memory modules
A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory...
US-1,003,2493 Longest element length determination in memory
Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises...
US-1,003,2492 Semiconductor device, driver IC, computer and electronic device
A semiconductor device that is novel, is capable of high-speed operation, consumes low power, or occupies a small area is provided. The semiconductor device...
US-1,003,2491 Apparatuses and methods for storing a data value in multiple columns
An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause...
US-1,003,2490 Sense amplifier layout for FinFET technology
A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a...
US-1,003,2489 Sensing amplifier to detect the memory cell current transition
This disclosure provides a method and apparatus for detecting a transition of a memory cell current from a first state to a second state. An example apparatus...
US-1,003,2488 System and method of managing data in a non-volatile memory having a staging sub-drive
A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory...
US-1,003,2487 One-time and multi-time programming using a correlated electron switch
An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to...
US-1,003,2486 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a first insulating layer; a global bit line and a reference bit line provided on the first...
US-1,003,2485 Multimedia distribution system
A multimedia file and methods of generating, distributing and using the multimedia file are described. Multimedia files in accordance with embodiments of the...
US-1,003,2484 Digital video builder system with designer-controlled user interaction
A digital video builder system with methodology for designer-controlled user interaction is described. In one embodiment, for example, a method comprises...
US-1,003,2483 Summary image browsing system and method
An embodiment of the present invention provides a summary image browsing system and method. A summary image browsing method of the present invention may...
US-1,003,2482 Moving image generating apparatus, moving image generating method and storage medium
A CPU extracts still images from image files recorded at predetermined time intervals among still images and moving images arbitrarily recorded in a...
US-1,003,2481 Speedy clipping
Provided is a system for efficiently creating snippets or clips from media assets without re-encoding the entire portion of already encoded media content...
US-1,003,2480 Motion tracking system
In a method of producing a composite animation live captured image sequence by capturing a live action sequence of action scenes with an image capture device,...
US-1,003,2479 Fingerprint-defined segment-based content delivery
Digital content, such as video, audio, multimedia, and similar files may be segmented at a determined frame resolution rate and analyzed to determine a...
US-1,003,2478 Video replay systems and methods
A video replay system which allows for the playback of video files from a buffer in random access memory and from disk to minimize the delay between capturing...
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