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Patent # Description
US-1,003,1870 Semiconductor device and control method thereof
According to one aspect, a module 11_1 includes a communication circuit 111 that performs data communication with an externally-provided control device 12...
US-1,003,1869 Cached memory structure and operation
In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data...
US-1,003,1868 Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and...
Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a...
US-1,003,1867 Pulse-latch based bus design for increased bandwidth
A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse...
US-1,003,1866 Information processing system, information processing device, information processing method, program and...
It is made possible for a user to set whether to download data used by a program without waiting for the acceptance of a download permission or download the...
US-1,003,1865 Memory system, storage device, and method for controlling memory system
To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a...
US-1,003,1864 Integrated circuit
A single device that provides computing system-level functionality with non-volatile storage controller functionality. These functionalities can share the same...
US-1,003,1863 Access controlled memory region
A first component associated with an access controlled memory region receives a transaction request including a protocol header from a second component. The...
US-1,003,1862 Memory protection unit, memory management unit, and microcontroller
A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured...
US-1,003,1861 Protect non-memory encryption engine (non-mee) metadata in trusted execution environment
A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in...
US-1,003,1860 Memory transfer of objects in a data storage device
Herein are data storage devices to transfer a data object between memory regions during a storage operation. These data storage devices include a host...
US-1,003,1859 Pulse counters
A method and apparatus of a device that reads and writes a plurality of counters is described. In an exemplary embodiment, a device receives plurality labels...
US-1,003,1858 Efficient translation reloads for page faults with host accelerator directly accessing process address space...
Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory...
US-1,003,1857 Address translation services for direct accessing of local memory over a network fabric
A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address...
US-1,003,1856 Common pointers in unified virtual memory system
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory...
US-1,003,1855 Fast data initialization
A method and system for fast file initialization is provided. An initialization request to create or extend a file is received. The initialization request...
US-1,003,1854 Memory system
A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer...
US-1,003,1853 Unified in-memory cache
In-memory caching can include providing, in a data node, a pinned memory space for caching data in a distributed file system. The data that is cached in the...
US-1,003,1852 Arithmetic processing apparatus and control method of the arithmetic processing apparatus
An arithmetic processing apparatus includes a prefetch unit configured to send a prefetch request to a subordinate cache memory for prefetching data of a main...
US-1,003,1851 Address re-ordering mechanism for efficient pre-fetch training in an out-of order processor
A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the...
US-1,003,1850 System and method to buffer data
A data storage device includes a controller, a non-volatile memory, and a buffer accessible to the controller. The buffer is configured to store data retrieved...
US-1,003,1849 Tracking alternative cacheline placement locations in a cache hierarchy
Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a...
US-1,003,1848 Method and apparatus for improving snooping performance in a multi-core multi-processor
A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where...
US-1,003,1847 System and method for replacement in associative memories using weighted PLRU trees
A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node...
US-1,003,1846 Transposition of two-dimensional arrays using single-buffering
The present embodiments relate to an address generator circuit for addressing a storage circuit. The address generator circuit may generate address signals for...
US-1,003,1845 Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device
Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a...
US-1,003,1844 NVS thresholding for efficient data management
For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by...
US-1,003,1843 Managing memory in a computer system
Methods, computer program products, and systems for managing memory in a computer system in which memory locations in use at any given time are represented as a...
US-1,003,1842 Method for adjusting the precision of a computer program manipulating at least one number with a decimal point
A method including measuring an initial precision measurement of at least one value of a number with a decimal point, measuring an infinite precision...
US-1,003,1841 Method and system for incrementally updating a test suite utilizing run-time application executions
The method includes capturing an execution scenario associated with a real-time execution of an application, determining at least one scenario variable based on...
US-1,003,1840 Method of ascertaining primary cause of memory consumption in program, and computer system and computer program...
A method of holding information for identifying a cause for an object becoming problematic and presenting the information to a user. The method ascertains the...
US-1,003,1839 Constraint extraction from natural language text for test data generation
A device may obtain text to be processed to extract constraints corresponding to an object in the text. The constraints may define values permitted to be...
US-1,003,1838 Predictive approach to environment provisioning
Embodiments of the present invention provide methods, systems, and computer program products for building an environment. Embodiments of the present invention...
US-1,003,1837 Dynamic service debugging in a virtual environment
A service oriented architecture (SOA) provides on-demand service call debugging and call stack tracing. The service call (e.g., an API) includes a new field and...
US-1,003,1836 Systems and methods for automatically generating message prototypes for accurate and efficient opaque service...
In a method of service emulation, a plurality of messages communicated between a system under test and a target system for emulation are recorded in a...
US-1,003,1835 Code block rating for guilty changelist identification and test script suggestion
Code block rating for guilty changelist identification and test script suggestion is discussed herein. An embodiment operates by assigning, by at least one...
US-1,003,1834 Cache-based tracing for time travel debugging and analysis
Recording a replay-able trace of execution of an executable entity using cache data includes executing one or more threads of the executable entity concurrently...
US-1,003,1833 Cache-based tracing for time travel debugging and analysis
Recording a replay-able trace of execution of an executable entity using cache data includes executing one or more threads of the executable entity concurrently...
US-1,003,1832 Dynamic sandboxing
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamic sandboxing. In one aspect, a method includes...
US-1,003,1831 Detecting causes of performance regression to adjust data systems
At least one application in a computing environment is executed and one or more performance metrics of the application are measured. The measured performance...
US-1,003,1830 Apparatus, system, and method for database management extensions
An apparatus, system, and method are provided for evaluating database accesses. The apparatus may comprise a computer program that causes a computer system to...
US-1,003,1829 Method and system for it resources performance analysis
There is disclosed a method of monitoring an infrastructure comprising managed units, the method comprising the steps of: acquiring data associated with a first...
US-1,003,1828 Optimization of power and computational density of a data center
Techniques for optimizing power and computational density of data centers are described. According to various embodiments, a benchmark test is performed by a...
US-1,003,1827 Assessment of processor performance metrics by monitoring probes constructed using instruction sequences
Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe...
US-1,003,1826 Self-healing charging device
Self-healing charging devices and techniques for identifying and/or troubleshooting causes of performance degradation in user devices are described. The...
US-1,003,1825 Electronic device having multiplexed input/output terminals
An electronic device has terminals for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver and...
US-1,003,1824 Self-diagnosis device and self-diagnosis method
A detailed execution schedule of self-diagnosis processing is set according to various requests. A self-diagnosis device includes a plurality of functional...
US-1,003,1823 Dangerous system command detection
Methods, computing systems and computer program products implement embodiments of the present invention that include defining, for a computer system, one or...
US-1,003,1822 Techniques for estimating ability of nodes to support high availability functionality in a storage cluster system
Various embodiments are generally directed to techniques for determining whether one node of a HA group is able to take over for another. An apparatus includes...
US-1,003,1821 Distributed network electronic interference abatement system and method
A system to protect and reconfigure a computer network in case of advance warning of a disruption event that would disrupt the operation of the computer network...
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