Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,003,8096 Three-dimensional finFET transistor with portion(s) of the fin channel removed in gate-last flow
A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping,...
US-1,003,8095 V-shape recess profile for embedded source/drain epitaxy
A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET...
US-1,003,8094 FinFET structure and methods thereof
A method and structure for providing a unique structure for FinFET S/D features described a semiconductor device including a substrate having a fin extending...
US-1,003,8093 FIN field effect transistors having liners between device isolation layers and active areas of the device
An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the...
US-1,003,8092 Three-level ferroelectric memory cell using band alignment engineering
A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The...
US-1,003,8091 Semiconductor device and method
The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped...
US-1,003,8090 Power MOSFETs and methods for forming the same
Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift...
US-1,003,8089 SGT MOSFET with adjustable CRSS and CISS
A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor...
US-1,003,8088 Power MOSFET having improved manufacturability, low on-resistance and high breakdown voltage
Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation...
US-1,003,8087 Semiconductor device and transistor cell having a diode region
According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in...
US-1,003,8086 Process for forming a high electron mobility transistor
A process of forming a High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials is disclosed. The process sequentially grows a buffer...
US-1,003,8085 High electron mobility transistor with carrier injection mitigation gate structure
A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for...
US-1,003,8084 Energy-filtered cold electron devices and methods
Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band...
US-1,003,8083 Semiconductor device with low band-to-band tunneling
The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source...
US-1,003,8082 Cascoded high voltage junction field effect transistor
A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the...
US-1,003,8081 Substrate contacts for a transistor
In some embodiments, a substrate contact is formed by forming a first gate structure and a second gate structure. The first gate structure is formed in a first...
US-1,003,8080 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with...
US-1,003,8079 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which...
US-1,003,8078 Integration process of finFET spacer formation
A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel...
US-1,003,8077 Method for fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is...
US-1,003,8076 Parasitic capacitance reducing contact structure in a finFET
In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into...
US-1,003,8075 Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes:...
US-1,003,8074 Manufacture method of TFT substrate and manufactured TFT substrate
The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first...
US-1,003,8073 3D integrated circuit device
A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors;...
US-1,003,8072 Threshold adjustment for quantum dot array devices with metal source and drain
Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the...
US-1,003,8071 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second...
US-1,003,8070 Nitride semiconductor device
A nitride semiconductor device according to the present invention includes a nitride semiconductor layer including an electron transit layer and an electron...
US-1,003,8069 Non-volatile memory device including charge trapping layer
A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate...
US-1,003,8068 Non-volatile memory device including nano floating gate
A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer...
US-1,003,8067 Spatially decoupled floating gate semiconductor device
A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a...
US-1,003,8066 Uniform vertical field effect transistor spacers
Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls,...
US-1,003,8065 Method of forming a semiconductor device with a gate contact positioned above the active region
One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a...
US-1,003,8064 Nitride semiconductor device
A nitride semiconductor device includes: a nitride semiconductor layer; a gate electrode finger having at least one end portion, and extending along a surface...
US-1,003,8063 Tunable breakdown voltage RF FET devices
A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an...
US-1,003,8062 Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of...
US-1,003,8061 High voltage laterally diffused MOSFET with buried field shield and method to fabricate same
A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the...
US-1,003,8060 Graphene NMOS transistor using nitrogen dioxide chemical adsorption
An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon....
US-1,003,8059 Semiconductor device
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and...
US-1,003,8058 FinFET device structure and method for forming same
A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin...
US-1,003,8057 Junction interlayer dielectric for reducing leakage current in semiconductor devices
A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the...
US-1,003,8056 Method for fabricating of cell pitch reduced semiconductor device and semiconductor device
A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a...
US-1,003,8055 Substrate structure with embedded layer for post-processing silicon handle elimination
The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure...
US-1,003,8054 Variable gate width for gate all-around transistors
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to...
US-1,003,8053 Methods for removal of selected nanowires in stacked gate all around architecture
A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first...
US-1,003,8052 Semiconductor device with channelstopper and method for producing the same
A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift...
US-1,003,8051 Vertical potential short in the periphery region of a III-nitride stack for preventing lateral leakage
A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and...
US-1,003,8050 FinFET resistor and method to fabricate same
A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of...
US-1,003,8049 Display device
A display device, includes a substrate; first to fourth subpixels sequentially arranged on the substrate; a first power line on a left side of the first...
US-1,003,8048 Display apparatus
A display apparatus and a method of manufacturing a display apparatus, the apparatus including a plurality of pixels on a substrate, wherein a first pixel of...
US-1,003,8047 Light emitting diode packaging structure and packaging method
The present application discloses a light emitting diode packaging structure comprising a base substrate; a metal lead on the base substrate; a cover plate; and...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.