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Patent # Description
US-1,003,8110 Solar cell backsheet and method for preparing same
Provided are a solar cell backsheet including a substrate layer and a blended resin layer including a fluorine-based resin and a (meth)acrylic-based copolymer...
US-1,003,8109 Silver solar cell contacts
Solar cell conductor formulations made are from two silver powders having different particle size distributions, an aluminum powder, and two frit glass...
US-1,003,8108 Glue bleeding prevention cap for optical sensor packages
One or more embodiments are directed to system in package (SiP) for optical devices, such as proximity sensing or optical ranging devices. One embodiment is...
US-1,003,8107 Enhanced photo-thermal energy conversion
Semiconducting quantum dots are applied to a fluid. The quantum dots are configured to absorb visible or near infrared light and re-radiate infrared energy that...
US-1,003,8106 Termination structure for gallium nitride Schottky diode
A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor...
US-1,003,8105 Semiconductor devices, a semiconductor diode and a method for forming a semiconductor device
A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure...
US-1,003,8104 Normally-off junction field-effect transistors and application to complementary circuits
A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a...
US-1,003,8102 Semiconductor device and method for manufacturing same
A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin...
US-1,003,8101 Memory cell and non-volatile semiconductor storage device
A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection...
US-1,003,8100 Semiconductor device
A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A...
US-1,003,8099 Semiconductor memory device
A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a...
US-1,003,8098 Method for manufacturing thin film transistor, thin film transistor and display panel
The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film...
US-1,003,8097 Light emitting diode display substrate, a method for manufacturing the same, and display device
A light emitting diode display substrate, a method of manufacturing the same, and a display device are provided. The method includes: forming a planarization...
US-1,003,8096 Three-dimensional finFET transistor with portion(s) of the fin channel removed in gate-last flow
A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping,...
US-1,003,8095 V-shape recess profile for embedded source/drain epitaxy
A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET...
US-1,003,8094 FinFET structure and methods thereof
A method and structure for providing a unique structure for FinFET S/D features described a semiconductor device including a substrate having a fin extending...
US-1,003,8093 FIN field effect transistors having liners between device isolation layers and active areas of the device
An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the...
US-1,003,8092 Three-level ferroelectric memory cell using band alignment engineering
A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The...
US-1,003,8091 Semiconductor device and method
The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped...
US-1,003,8090 Power MOSFETs and methods for forming the same
Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift...
US-1,003,8089 SGT MOSFET with adjustable CRSS and CISS
A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor...
US-1,003,8088 Power MOSFET having improved manufacturability, low on-resistance and high breakdown voltage
Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation...
US-1,003,8087 Semiconductor device and transistor cell having a diode region
According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in...
US-1,003,8086 Process for forming a high electron mobility transistor
A process of forming a High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials is disclosed. The process sequentially grows a buffer...
US-1,003,8085 High electron mobility transistor with carrier injection mitigation gate structure
A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for...
US-1,003,8084 Energy-filtered cold electron devices and methods
Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band...
US-1,003,8083 Semiconductor device with low band-to-band tunneling
The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source...
US-1,003,8082 Cascoded high voltage junction field effect transistor
A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the...
US-1,003,8081 Substrate contacts for a transistor
In some embodiments, a substrate contact is formed by forming a first gate structure and a second gate structure. The first gate structure is formed in a first...
US-1,003,8080 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with...
US-1,003,8079 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which...
US-1,003,8078 Integration process of finFET spacer formation
A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel...
US-1,003,8077 Method for fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is...
US-1,003,8076 Parasitic capacitance reducing contact structure in a finFET
In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into...
US-1,003,8075 Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes:...
US-1,003,8074 Manufacture method of TFT substrate and manufactured TFT substrate
The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first...
US-1,003,8073 3D integrated circuit device
A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors;...
US-1,003,8072 Threshold adjustment for quantum dot array devices with metal source and drain
Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the...
US-1,003,8071 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second...
US-1,003,8070 Nitride semiconductor device
A nitride semiconductor device according to the present invention includes a nitride semiconductor layer including an electron transit layer and an electron...
US-1,003,8069 Non-volatile memory device including charge trapping layer
A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate...
US-1,003,8068 Non-volatile memory device including nano floating gate
A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer...
US-1,003,8067 Spatially decoupled floating gate semiconductor device
A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a...
US-1,003,8066 Uniform vertical field effect transistor spacers
Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls,...
US-1,003,8065 Method of forming a semiconductor device with a gate contact positioned above the active region
One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a...
US-1,003,8064 Nitride semiconductor device
A nitride semiconductor device includes: a nitride semiconductor layer; a gate electrode finger having at least one end portion, and extending along a surface...
US-1,003,8063 Tunable breakdown voltage RF FET devices
A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an...
US-1,003,8062 Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of...
US-1,003,8061 High voltage laterally diffused MOSFET with buried field shield and method to fabricate same
A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the...
US-1,003,8060 Graphene NMOS transistor using nitrogen dioxide chemical adsorption
An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon....
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