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Patent # Description
US-1,003,8008 Integrated structures and NAND memory arrays
Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include...
US-1,003,8007 Three-dimensional semiconductor devices
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor...
US-1,003,8006 Through-memory-level via structures for a three-dimensional memory device
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
US-1,003,8005 Sense circuit having bit line clamp transistors with different threshold voltages for selectively boosting...
Techniques are provided to boost current in channels of memory strings during sensing operations based on a data pattern or a pattern of physical...
US-1,003,8004 NAND memory cell string having a stacked select gate structure and process for for forming same
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each...
US-1,003,8003 Single-poly nonvolatile memory cell structure having an erase device
A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor...
US-1,003,8002 Semiconductor devices and methods of fabrication
Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a...
US-1,003,8001 Hybrid electrically erasable programmable read-only memory (EEPROM) systems and methods for forming
Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a...
US-1,003,8000 Memory cell and fabricating method thereof
A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line...
US-1,003,7999 Semiconductor device including landing pad for connecting substrate and capacitor
A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of...
US-1,003,7998 Semiconductor structures with deep trench capacitor and methods of manufacture
An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures...
US-1,003,7997 Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the...
A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a...
US-1,003,7996 Semiconductor device includes a substrate having conductive contact structures thereon
A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second...
US-1,003,7995 Semiconductor device and a method for fabricating the same
A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and...
US-1,003,7994 Semiconductor devices having Fin field effect transistor (FinFET) structures and manufacturing and design...
Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed...
US-1,003,7993 Method of making a FinFET device
A semiconductor device includes a semiconductor substrate; an isolation region over the semiconductor substrate; and two fin features over the semiconductor...
US-1,003,7992 Methods and apparatuses for optimizing power and functionality in transistors
A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled...
US-1,003,7991 Systems and methods for fabricating FinFETs with different threshold voltages
Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin...
US-1,003,7990 Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer
A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending...
US-1,003,7989 III-V lateral bipolar integration with silicon
A method of manufacturing a semiconductor structure is provided. Spacers on sidewalls of mandrels in a bipolar junction transistor (BJT) region, fins and...
US-1,003,7988 High voltage PNP using isolation for ESD and method for producing the same
A method of forming a HV lateral PNP BJT with a pulled back isolation structure and a polysilicon gate covering a part of the NW+HVNDDD base region and a part...
US-1,003,7987 Semiconductor structure of ESD protection device and method for manufacturing the same
Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a...
US-1,003,7986 ESD protection structure and method of fabrication thereof
An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second...
US-1,003,7985 Compound micro-transfer-printed power transistor device
Embodiments of the present invention provide a compound power transistor device including a first semiconductor substrate including a first semiconductor...
US-1,003,7984 Display device
A display device including: a substrate including a display area and a non-display area; a first pad terminal and a second pad terminal disposed in the...
US-1,003,7983 Semiconductor device with modified current distribution
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a...
US-1,003,7982 Photonic integrated circuit package
Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including multiple electrodes...
US-1,003,7981 Integrated display system with multi-color light emitting diodes (LEDs)
A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a...
US-1,003,7980 Fabricating method of a semiconductor light emitting device
A fabricating method of a semiconductor light emitting device includes disposing a plurality of non-conductive walls on a substrate. An alignment position is...
US-1,003,7979 Surface-mountable multi-chip component
A surface-mountable multi-chip component includes a carrier having a first connection element, a second connection element and third connection element that are...
US-1,003,7978 Semiconductor module and stack arrangement of semiconductor modules
A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a...
US-1,003,7977 Power electronics system
A power electronics assembly includes a case and an array of power stages disposed within the case. Each of the power stages includes a transistor-based...
US-1,003,7976 Scalable package architecture and associated techniques and configurations
Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and...
US-1,003,7975 Semiconductor device package and a method of manufacturing the same
A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on...
US-1,003,7974 Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package...
US-1,003,7973 Method for manufacturing semiconductor package structure
A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the...
US-1,003,7972 Electronic module comprising fluid cooling channel and method of manufacturing the same
Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an...
US-1,003,7971 Semiconductor device having plural memory chip
A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses...
US-1,003,7970 Multiple interconnections between die
Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a...
US-1,003,7969 Integrated circuit structure with active and passive devices in different tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a...
US-1,003,7968 Alignment systems and wafer bonding systems and methods
Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes...
US-1,003,7967 Injection molded solder bumping
Methods for depositing material on a chip include forming a mold layer on a substrate. The mold layer has one or more openings over respective contact areas on...
US-1,003,7966 Semiconductor device and manufacturing method therefor
The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip...
US-1,003,7965 Semiconductor device having a protective material with a first pH formed around cooper wire bonds and aluminum...
A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto...
US-1,003,7964 Die-packaging component with retaining structure for package body thereof
A die-packaging component includes a substrate, a die, a jumper structure, a lead structure and a package body. The substrate has a base surface further...
US-1,003,7963 Package structure and method of forming the same
A package structure and method of forming the same includes: a first package including: a first die; a via adjacent the first die; a molding compound...
US-1,003,7962 Ball height control in bonding process
A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package...
US-1,003,7961 Integrated fan-out package and method of fabricating the same
An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit...
US-1,003,7960 Connection structure and connecting method of circuit member
There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a...
US-1,003,7959 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is...
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