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Patent # Description
US-1,003,7958 Fabrication of solder balls with injection molded solder
Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution...
US-1,003,7957 Semiconductor device and method of manufacturing thereof
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of...
US-1,003,7956 Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method...
The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal...
US-1,003,7955 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
US-1,003,7954 Chip with I/O pads on peripheries and method making the same
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; a first metal layer, formed above the...
US-1,003,7953 Contact pad for semiconductor devices
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
US-1,003,7952 Integrated circuit, electronic device and method for transmitting data in electronic device
An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a...
US-1,003,7951 Semiconductor package with antenna
A semiconductor package includes a radio frequency (RF) module, an antenna, an electromagnetic (EM) shield and a first mold body. The RF module having a bottom...
US-1,003,7950 Semiconductor device having features to prevent reverse engineering
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that...
US-1,003,7949 Semiconductor package and fabricating method thereof
A semiconductor package that includes EMI shielding and a fabricating method thereof are disclosed. In one embodiment, the fabricating method of a semiconductor...
US-1,003,7948 Invisible compartment shielding
A method for shielding a compartment in a module of an electronic device includes molding the module using a mold material that activates when a laser is...
US-1,003,7947 Electronic devices with yielding substrates
In accordance with certain embodiments, a light-emitting element composed of one or more discrete units configured for light emission is adhered directly to a...
US-1,003,7946 Package structure having embedded bonding film and manufacturing method thereof
A package structure having an embedded bonding film including a redistribution substrate, a bonding film and a core is provided. The redistribution substrate...
US-1,003,7945 Package structure and three dimensional package structure
A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the...
US-1,003,7944 Self-aligned contact process enabled by low temperature
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal...
US-1,003,7943 Metal gate transistor and fabrication method thereof
A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate and...
US-1,003,7942 Low resistance contact structures for trench structures
An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel...
US-1,003,7941 Integrated device package comprising photo sensitive fill between a substrate and a die
An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first...
US-1,003,7940 Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an...
US-1,003,7939 Semiconductor apparatus
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance...
US-1,003,7938 Semiconductor packages
A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a...
US-1,003,7937 Method for forming semiconductor package
A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface,...
US-1,003,7936 Semiconductor package with coated bonding wires and fabrication method thereof
A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires...
US-1,003,7935 Lead frame with dummy leads for burr mitigation during encapsulation
Embodiments of a lead frame for a packaged semiconductor device are provided, one embodiment including: a die pad; a first row of active lead fingers that are...
US-1,003,7934 Semiconductor chip package having contact pins at short side edges
A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact...
US-1,003,7933 Test socket assembly and related methods
A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more...
US-1,003,7932 Semiconductor device and method of manufacturing the same
In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having...
US-1,003,7931 3D-microstrip branchline coupler
The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture....
US-1,003,7930 Power semiconductor module and manufacturing method of power semiconductor module
An object of the present invention is to provide a power semiconductor module that can secure a satisfactory cooling without expanding the size of a case...
US-1,003,7929 Thermally enhanced semiconductor package having field effect transistors with back-gate feature
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally...
US-1,003,7928 Circuit board and electronic device
A circuit board includes a metal circuit plate, a metallic heat diffusing plate disposed below the metal circuit plate and having an upper surface and a lower...
US-1,003,7927 Semiconductor structure, testing and fabricating method thereof
A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first...
US-1,003,7926 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-1,003,7925 Removable sacrificial connections for semiconductor devices
Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor...
US-1,003,7924 Fin-FET device and fabrication method thereof
A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type...
US-1,003,7923 Forming transistor by selectively growing gate spacer
A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode...
US-1,003,7922 Co-integration of tensile silicon and compressive silicon germanium
Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include ...
US-1,003,7921 Structure and formation method of fin-like field effect transistor
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over...
US-1,003,7920 Method for semiconductor device fabrication
A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate...
US-1,003,7919 Integrated single-gated vertical field effect transistor (VFET) and independent double-gated VFET
A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom...
US-1,003,7918 Contact structure and method of fabricating the same
A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a...
US-1,003,7917 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
US-1,003,7916 Semiconductor fins for finFET devices and sidewall image transfer (SIT) processes for manufacturing the same
A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the...
US-1,003,7915 Fabricating method of a semiconductor structure with an epitaxial layer
A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate...
US-1,003,7914 Semiconductor transistor device and fabrication method thereof
A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a...
US-1,003,7913 Interconnect structures with enhanced electromigration resistance
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction...
US-1,003,7912 Semiconductor device and method of manufacturing the same
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain...
US-1,003,7911 Device layer transfer with a preserved handle wafer section
Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and...
US-1,003,7910 Wafer holder and method for manufacturing the same
A wafer holder 10 includes a resin adhesive layer 16 between a ceramic electrostatic chuck 12 and a metal cooling plate 14. The adhesive layer 16 includes a...
US-1,003,7909 Plasma processing apparatus
In a plasma processing apparatus, a connector section with the film-like electrode of a sintered plate of a sample stage to which high-frequency power is...
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