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Patent # Description
US-1,004,3787 Optoelectronic chip embedded organic substrate
Optoelectronic devices and method of forming the same include an optoelectronic chip in a substrate layer, the optoelectronic chip having one or more...
US-1,004,3786 Composite protection circuit, composite protection element, and LED device for illumination
A Zener diode used as an ESD protection element is connected in parallel to a circuit to be protected, for example an LED chip. The Zener diode is connected in...
US-1,004,3785 Light emitting device
A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of...
US-1,004,3784 Light emitting device reflective bank structure
Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the...
US-1,004,3783 LED spirit system and manufacturing method
The present invention relates to a new method, system and apparatus for light emitting diode (LED) packages. An object of the present invention is to provide an...
US-1,004,3782 Electronic device package having a dielectric layer and an encapsulant
A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip...
US-1,004,3781 3D semiconductor device and structure
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer...
US-1,004,3780 Semiconductor package
A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first...
US-1,004,3779 Packaged microelectronic device for a package-on-package device
Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device ("PoP") with enhanced tolerance for warping. In...
US-1,004,3778 Methods of packaging semiconductor devices and packaged semiconductor devices
Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device...
US-1,004,3777 Display device
A display device comprises: control circuit substrates disposed in a rear surface of a display panel, a control circuit that generates a control signal in order...
US-1,004,3776 Micro device transfer system with pivot mount
A micro pick up array mount includes a pivot platform to allow a micro pick up array to automatically align with a carrier substrate. Deflection of the pivot...
US-1,004,3775 Bonding material, bonding method and semiconductor device for electric power
The present invention has an object to achieve bonding which satisfies both in heat resistivity and in stress-relaxation ability, and the bonding material...
US-1,004,3774 Integrated circuit packaging substrate, semiconductor package, and manufacturing method
An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one...
US-1,004,3773 Semiconductor device and semiconductor device manufacturing method
The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions...
US-1,004,3772 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first...
US-1,004,3771 Semiconductor device with insulation layers
A semiconductor device includes a semiconductor chip, a terminal layer, an insulation layer with an opening, a protection layer with an opening, an inner...
US-1,004,3770 System and method for an improved interconnect structure
Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and...
US-1,004,3769 Semiconductor devices including dummy chips
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first...
US-1,004,3768 Semiconductor device and method of manufacture thereof
A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a...
US-1,004,3767 Semiconductor device including dummy conductive cells
A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a...
US-1,004,3766 Protected integrated circuit
The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first...
US-1,004,3765 Damaging integrated circuit components
An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The...
US-1,004,3764 Through silicon via device having low stress, thin film gaps and methods for forming the same
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a "buffer zone" or gap layer...
US-1,004,3763 Shielded lead frame packages
Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency (RF)...
US-1,004,3762 Semiconductor device
A semiconductor device includes a plurality of semiconductor elements including a power semiconductor element, a lead frame including one main surface on which...
US-1,004,3761 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is...
US-1,004,3760 Registration mark formation during sidewall image transfer process
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...
US-1,004,3759 Overlay mark
An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in...
US-1,004,3758 Fan-out semiconductor package
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing...
US-1,004,3757 Semiconductor package structure and method of fabricating the same
A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing...
US-1,004,3756 Local phase correction
The present invention is directed to integrated circuits and methods thereof. More specifically, embodiments of the present invention provide a local correction...
US-1,004,3755 Electronic device
An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a...
US-1,004,3754 Semiconductor device having air gap structures and method of fabricating thereof
A device having a conductive feature disposed on a substrate; a cap structure is disposed on top of the conductive feature and on at least two sidewalls of the...
US-1,004,3753 Airgaps to isolate metallization features
The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The...
US-1,004,3752 Substrate contact using dual sided silicidation
An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a...
US-1,004,3751 Three dimensional storage cell array with highly dense and scalable word line design approach
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having...
US-1,004,3750 Nanotube structure based metal damascene process
In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups...
US-1,004,3749 Semiconductor device
Provided is a semiconductor device in which a fuse element, which is cuttable by a laser, can be stably cut. The fuse element includes an upper fuse element, a...
US-1,004,3748 Vertically integrated nanosheet fuse
Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet...
US-1,004,3747 Vertical fuse structures
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
US-1,004,3746 Fabrication of vertical fuses from vertical fins
A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction...
US-1,004,3745 Semiconductor package devices integrated with inductor
The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface,...
US-1,004,3744 Avoiding gate metal via shorting to source or drain contacts
Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The...
US-1,004,3743 Semiconductor device and method of producing semiconductor device
A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second...
US-1,004,3742 Semiconductor device
In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween....
US-1,004,3741 Low-dispersion component in an electronic chip
A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components...
US-1,004,3740 Package with passivated interconnects
Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may...
US-1,004,3739 Semiconductor device and leadframe
A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the...
US-1,004,3738 Integrated package assembly for switching regulator
In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an...
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