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Patent # Description
US-1,004,3737 Chip on film package
A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first...
US-1,004,3736 Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting...
US-1,004,3735 Semiconductor module, semiconductor device, and method for manufacturing semiconductor devices
A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises:...
US-1,004,3734 Method and device for vacuum reacting force soldering
The present invention discloses a vacuum reacting force soldering method, comprising the following steps: die-bonding a chip onto a substrate through soldering...
US-1,004,3733 Integrated circuit packaging system and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming...
US-1,004,3732 Heat sink
The heat sink is a body or block of solid-phase gallium having a plurality of sealed cavities defined therein containing an unencapsulated phase change material...
US-1,004,3731 Multi-step processes for high temperature bonding and bonded substrates formed therefrom
A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the...
US-1,004,3730 Stacked silicon package assembly having an enhanced lid
A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is...
US-1,004,3729 Power electronics module
A power electronics module and a method of manufacturing a power electronics module and a base plate. The power electronics module comprising at least one power...
US-1,004,3728 Semiconductor package structure and manufacturing method thereof
A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a...
US-1,004,3727 Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is an...
US-1,004,3726 Embedded component substrate with a metal core layer having an open cavity and pad electrodes at the bottom of...
An embedded component substrate includes: a core layer; a first electrode provided on a top surface of the core layer with a first insulating layer ...
US-1,004,3725 Flip chip ball grid array with low impedence and grounded lid
A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises...
US-1,004,3724 Using an integrated circuit die for multiple devices
In an example, a semiconductor assembly includes an integrated circuit (IC) die. The IC die includes a first region that includes a programmable fabric; a...
US-1,004,3723 Method of forming a temporary test structure for device fabrication
A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during...
US-1,004,3722 Method for testing semiconductor wafers using temporary sacrificial bond pads
A method is provided for testing a semiconductor wafer, including individual semiconductor devices located on the semiconductor wafer, using temporary...
US-1,004,3721 Method of manufacturing semiconductor device having semiconductor chip mounted on lead frame
In the manufacture of a semiconductor device using a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner...
US-1,004,3720 Systems and methods for interconnect simulation and characterization
Exemplary systems and methods allow for precise formation and subsequent characterization of electrical interconnects, for example solder joints associated with...
US-1,004,3719 Semiconductor wafer evaluation method and semiconductor wafer manufacturing method
A semiconductor-wafer evaluation method includes: before the mirror-polishing step, measuring warp data of displacement of the surface of the semiconductor...
US-1,004,3718 Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a...
US-1,004,3717 Electronic device
An electronic device includes at least two boards and support pillars. The at least two boards include hole portions. The support pillars inserted into the hole...
US-1,004,3716 N-well/P-well strap structures
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating...
US-1,004,3715 Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure...
US-1,004,3714 Elongated contacts using litho-freeze-litho-etch process
A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which...
US-1,004,3713 Method to reduce FinFET short channel gate height
Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over...
US-1,004,3712 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, at least two gate spacers, a gate stack, an insulating structure, and at least one sacrificial layer. The...
US-1,004,3711 Contact resistance reduction by III-V Ga deficient surface
A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate....
US-1,004,3710 Active matrix organic light emitting diode array substrate, fabricating method, and display apparatus
In some embodiments of the disclosed subject matter provides an active matrix organic light emitting diode array substrate, comprising; multiple pixel units in...
US-1,004,3709 Methods for thermally forming a selective cobalt layer
Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing...
US-1,004,3708 Structure and method for capping cobalt contacts
A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in...
US-1,004,3707 Additive conductor redistribution layer (ACRL)
A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the...
US-1,004,3706 Mitigating pattern collapse
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is...
US-1,004,3705 Memory device and method of forming thereof
A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric...
US-1,004,3704 MEMS grid for manipulating structural parameters of MEMS devices
A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device,...
US-1,004,3703 Apparatus and method for forming interconnection lines having variable pitch and variable widths
A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having...
US-1,004,3702 Manufacturing method for semiconductor device and semiconductor device
A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm, in...
US-1,004,3701 Substrate removal from a carrier
Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is...
US-1,004,3700 Method of fabricating diamond-semiconductor composite substrates
A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a...
US-1,004,3699 High capacity overhead transport (OHT) rail system with multiple levels
An overhead transport (OHT) system with multiple levels of rails for the transport of semiconductor workpieces is provided. A first vehicle is configured to...
US-1,004,3698 Transport system and transport method
In a transport system, a local track is disposed so as to be below an overhead travelling vehicle track in parallel or substantially in parallel therewith, and...
US-1,004,3697 Substrate processing apparatus and article manufacturing method
A substrate processing apparatus including a plurality of processing devices each of which processes a substrate is provided. The apparatus comprises a...
US-1,004,3696 Wafer container with tubular environmental control components
A wafer container utilizes a rigid polymer tubular tower with slots and a "getter" therein for absorbing and filtering moisture and vapors within the wafer...
US-1,004,3695 Apparatus for carrying and shielding wafers
Apparatus for carrying and shielding wafers includes a wafer container, a plurality of wafer cassettes disposed in the wafer container, and an engaging lock...
US-1,004,3694 Inspection device and substrate processing apparatus
Surface image data of a non-defective sample substrate is acquired, and surface image data of a substrate to be inspected is acquired. Differences between...
US-1,004,3693 Method and apparatus for handling substrates in a processing system having a buffer chamber
Implementations described herein generally relate to a method and apparatus for processing substrates in a processing system. The method includes identifying,...
US-1,004,3692 Substrate processing apparatus, substrate transport method, and computer-readable recording medium with stored...
A substrate processing apparatus includes a substrate processing device, a substrate accommodation-status detection device, a substrate-transport device...
US-1,004,3691 Control wafer making device
A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In...
US-1,004,3690 Fault detection using showerhead voltage variation
A method includes providing radio frequency (RF) power from an RF power supply to a showerhead of a plasma processing system running a process operation on a...
US-1,004,3689 Chamber apparatus and processing system
A chamber apparatus according to the present invention including a chamber main body including an opening portion in an upper surface; a door that opens/closes...
US-1,004,3688 Method for mount tape die release system for thin die ejection
An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to...
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