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Patent # Description
US-1,004,3823 Semiconductor device
According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first...
US-1,004,3822 Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts
A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the...
US-1,004,3818 Semiconductor devices including stacked electrodes
Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first and...
US-1,004,3810 Dynamic random access memory and method of fabricating the same
A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a plurality of isolation structures, a plurality of word lines, a plurality...
US-1,004,3809 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line...
US-1,004,3808 Semiconductor memory
According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a...
US-1,004,3805 Method to induce strain in finFET channels from an adjacent region
Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different...
US-1,004,3803 Semiconductor device having gate electrodes with stacked metal layers
A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of...
US-1,004,3801 Air gap spacer for metal gates
A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and...
US-1,004,3800 Integrated circuit device with gate line crossing fin-type active region
An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active...
US-1,004,3796 Vertically stacked nanowire field effect transistors
A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire...
US-1,004,3792 Electrostatic protection device
An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a...
US-1,004,3790 Diode device of transient voltage suppressor and manufacturing method thereof
A diode device of a transient voltage suppressor (TVS) is disclosed. The diode device includes a substrate, a first well, a second well, a first electrode and a...
US-1,004,3789 Semiconductor packages including an adhesive pattern
A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first...
US-1,004,3787 Optoelectronic chip embedded organic substrate
Optoelectronic devices and method of forming the same include an optoelectronic chip in a substrate layer, the optoelectronic chip having one or more...
US-1,004,3786 Composite protection circuit, composite protection element, and LED device for illumination
A Zener diode used as an ESD protection element is connected in parallel to a circuit to be protected, for example an LED chip. The Zener diode is connected in...
US-1,004,3785 Light emitting device
A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of...
US-1,004,3784 Light emitting device reflective bank structure
Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the...
US-1,004,3783 LED spirit system and manufacturing method
The present invention relates to a new method, system and apparatus for light emitting diode (LED) packages. An object of the present invention is to provide an...
US-1,004,3782 Electronic device package having a dielectric layer and an encapsulant
A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip...
US-1,004,3781 3D semiconductor device and structure
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer...
US-1,004,3780 Semiconductor package
A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first...
US-1,004,3779 Packaged microelectronic device for a package-on-package device
Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device ("PoP") with enhanced tolerance for warping. In...
US-1,004,3778 Methods of packaging semiconductor devices and packaged semiconductor devices
Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device...
US-1,004,3777 Display device
A display device comprises: control circuit substrates disposed in a rear surface of a display panel, a control circuit that generates a control signal in order...
US-1,004,3776 Micro device transfer system with pivot mount
A micro pick up array mount includes a pivot platform to allow a micro pick up array to automatically align with a carrier substrate. Deflection of the pivot...
US-1,004,3775 Bonding material, bonding method and semiconductor device for electric power
The present invention has an object to achieve bonding which satisfies both in heat resistivity and in stress-relaxation ability, and the bonding material...
US-1,004,3774 Integrated circuit packaging substrate, semiconductor package, and manufacturing method
An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one...
US-1,004,3773 Semiconductor device and semiconductor device manufacturing method
The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions...
US-1,004,3772 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first...
US-1,004,3771 Semiconductor device with insulation layers
A semiconductor device includes a semiconductor chip, a terminal layer, an insulation layer with an opening, a protection layer with an opening, an inner...
US-1,004,3770 System and method for an improved interconnect structure
Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and...
US-1,004,3769 Semiconductor devices including dummy chips
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first...
US-1,004,3768 Semiconductor device and method of manufacture thereof
A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a...
US-1,004,3767 Semiconductor device including dummy conductive cells
A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a...
US-1,004,3766 Protected integrated circuit
The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first...
US-1,004,3765 Damaging integrated circuit components
An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The...
US-1,004,3764 Through silicon via device having low stress, thin film gaps and methods for forming the same
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a "buffer zone" or gap layer...
US-1,004,3763 Shielded lead frame packages
Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency (RF)...
US-1,004,3762 Semiconductor device
A semiconductor device includes a plurality of semiconductor elements including a power semiconductor element, a lead frame including one main surface on which...
US-1,004,3761 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is...
US-1,004,3760 Registration mark formation during sidewall image transfer process
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...
US-1,004,3759 Overlay mark
An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in...
US-1,004,3758 Fan-out semiconductor package
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing...
US-1,004,3757 Semiconductor package structure and method of fabricating the same
A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing...
US-1,004,3756 Local phase correction
The present invention is directed to integrated circuits and methods thereof. More specifically, embodiments of the present invention provide a local correction...
US-1,004,3755 Electronic device
An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a...
US-1,004,3754 Semiconductor device having air gap structures and method of fabricating thereof
A device having a conductive feature disposed on a substrate; a cap structure is disposed on top of the conductive feature and on at least two sidewalls of the...
US-1,004,3753 Airgaps to isolate metallization features
The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The...
US-1,004,3752 Substrate contact using dual sided silicidation
An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a...
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