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Patent # Description
US-1,004,3751 Three dimensional storage cell array with highly dense and scalable word line design approach
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having...
US-1,004,3750 Nanotube structure based metal damascene process
In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups...
US-1,004,3749 Semiconductor device
Provided is a semiconductor device in which a fuse element, which is cuttable by a laser, can be stably cut. The fuse element includes an upper fuse element, a...
US-1,004,3748 Vertically integrated nanosheet fuse
Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet...
US-1,004,3747 Vertical fuse structures
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
US-1,004,3746 Fabrication of vertical fuses from vertical fins
A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction...
US-1,004,3745 Semiconductor package devices integrated with inductor
The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface,...
US-1,004,3744 Avoiding gate metal via shorting to source or drain contacts
Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The...
US-1,004,3743 Semiconductor device and method of producing semiconductor device
A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second...
US-1,004,3742 Semiconductor device
In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween....
US-1,004,3741 Low-dispersion component in an electronic chip
A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components...
US-1,004,3740 Package with passivated interconnects
Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may...
US-1,004,3739 Semiconductor device and leadframe
A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the...
US-1,004,3738 Integrated package assembly for switching regulator
In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an...
US-1,004,3737 Chip on film package
A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first...
US-1,004,3736 Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting...
US-1,004,3735 Semiconductor module, semiconductor device, and method for manufacturing semiconductor devices
A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises:...
US-1,004,3734 Method and device for vacuum reacting force soldering
The present invention discloses a vacuum reacting force soldering method, comprising the following steps: die-bonding a chip onto a substrate through soldering...
US-1,004,3733 Integrated circuit packaging system and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming...
US-1,004,3732 Heat sink
The heat sink is a body or block of solid-phase gallium having a plurality of sealed cavities defined therein containing an unencapsulated phase change material...
US-1,004,3731 Multi-step processes for high temperature bonding and bonded substrates formed therefrom
A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the...
US-1,004,3730 Stacked silicon package assembly having an enhanced lid
A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is...
US-1,004,3729 Power electronics module
A power electronics module and a method of manufacturing a power electronics module and a base plate. The power electronics module comprising at least one power...
US-1,004,3728 Semiconductor package structure and manufacturing method thereof
A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a...
US-1,004,3727 Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is an...
US-1,004,3726 Embedded component substrate with a metal core layer having an open cavity and pad electrodes at the bottom of...
An embedded component substrate includes: a core layer; a first electrode provided on a top surface of the core layer with a first insulating layer ...
US-1,004,3725 Flip chip ball grid array with low impedence and grounded lid
A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises...
US-1,004,3724 Using an integrated circuit die for multiple devices
In an example, a semiconductor assembly includes an integrated circuit (IC) die. The IC die includes a first region that includes a programmable fabric; a...
US-1,004,3723 Method of forming a temporary test structure for device fabrication
A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during...
US-1,004,3722 Method for testing semiconductor wafers using temporary sacrificial bond pads
A method is provided for testing a semiconductor wafer, including individual semiconductor devices located on the semiconductor wafer, using temporary...
US-1,004,3721 Method of manufacturing semiconductor device having semiconductor chip mounted on lead frame
In the manufacture of a semiconductor device using a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner...
US-1,004,3720 Systems and methods for interconnect simulation and characterization
Exemplary systems and methods allow for precise formation and subsequent characterization of electrical interconnects, for example solder joints associated with...
US-1,004,3719 Semiconductor wafer evaluation method and semiconductor wafer manufacturing method
A semiconductor-wafer evaluation method includes: before the mirror-polishing step, measuring warp data of displacement of the surface of the semiconductor...
US-1,004,3718 Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a...
US-1,004,3717 Electronic device
An electronic device includes at least two boards and support pillars. The at least two boards include hole portions. The support pillars inserted into the hole...
US-1,004,3716 N-well/P-well strap structures
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating...
US-1,004,3715 Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure...
US-1,004,3714 Elongated contacts using litho-freeze-litho-etch process
A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which...
US-1,004,3713 Method to reduce FinFET short channel gate height
Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over...
US-1,004,3712 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, at least two gate spacers, a gate stack, an insulating structure, and at least one sacrificial layer. The...
US-1,004,3711 Contact resistance reduction by III-V Ga deficient surface
A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate....
US-1,004,3710 Active matrix organic light emitting diode array substrate, fabricating method, and display apparatus
In some embodiments of the disclosed subject matter provides an active matrix organic light emitting diode array substrate, comprising; multiple pixel units in...
US-1,004,3709 Methods for thermally forming a selective cobalt layer
Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing...
US-1,004,3708 Structure and method for capping cobalt contacts
A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in...
US-1,004,3707 Additive conductor redistribution layer (ACRL)
A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the...
US-1,004,3706 Mitigating pattern collapse
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is...
US-1,004,3705 Memory device and method of forming thereof
A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric...
US-1,004,3704 MEMS grid for manipulating structural parameters of MEMS devices
A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device,...
US-1,004,3703 Apparatus and method for forming interconnection lines having variable pitch and variable widths
A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having...
US-1,004,3702 Manufacturing method for semiconductor device and semiconductor device
A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm, in...
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