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Patent # Description
US-1,005,0661 Modem and RF chips, application processor including the same and operating method thereof
A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the...
US-1,005,0660 Electronic device with radio function and operating method thereof
A method and a device for selecting a radio in an electronic device with a hybrid radio function. The method includes detecting an entrance to a hybrid radio...
US-1,005,0659 Systems and methods for non-linear digital self-interference cancellation
A system and method for non-linear digital self-interference cancellation including a pre-processor that generates a first pre-processed digital transmit signal...
US-1,005,0658 Docking sleeve with electrical adapter
A protective arrangement for an electronic device includes a flexible cover having a panel and a skirt that form an interior cavity to receive an electronic...
US-1,005,0657 System and method for pairing a UICC card with a particular mobile communications device
A method pairs a mobile communications device card with a mobile device responsive to an actuation of the mobile device. The mobile communications device card...
US-1,005,0656 Small form-factor pluggable transceiver
A small form-factor pluggable (SFP) transceiver provided for being inserted into an electrical connection slot includes a housing, two electrical signal...
US-1,005,0655 Distributed digitally convertible radio (DDCR)
Embodiments of a hybrid unit that supports a configurable number of radio units for a base station in a cellular communications network and embodiments of...
US-1,005,0654 Method and system for suppressing a parasite signal received by a satellite payload
A method for suppressing a parasite signal received with a useful signal by a network of elementary antennas of a payload of a satellite. The suppression method...
US-1,005,0653 Circuits and methods related to switchless carrier aggregation in radio-frequency receivers
Circuits and methods related to switchless carrier aggregation in radio-frequency receivers. In some embodiments, a carrier aggregation (CA) circuit can include...
US-1,005,0652 Device and method for enhancing interference rejection by treating separated signal streams as diversity branches
An apparatus and a method are provided. The solution includes controlling the reception of a signal; dividing the received signal into a predetermined number of...
US-1,005,0651 Wireless communication system and method
A marine propulsor comprises: a stationary part and a movable part which is movable relative to the stationary part; and a wireless communication system,...
US-1,005,0650 Method, apparatus, and computer program product improving registration with real time location services
An example disclosed method for registering an unregistered radio frequency (RF) location tag carried by a participant includes receiving blink data from an...
US-1,005,0649 Communication devices and methods
Devices and methods are provided where a first signal is provided via an interface, and a second signal is provided related to the suitability of the first...
US-1,005,0648 Transmitter circuit and method for digital satellite equipment control
Satellite controller circuitry includes a connection (i.e. coaxial or single wire with ground), with a control unit receiving a data message and generating a...
US-1,005,0647 Power amplification module
A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector...
US-1,005,0646 Amplifier adjusting device, system including an amplifier adjusting device and method for operating an...
The present invention describes an amplifier adjusting device for an amplifier element which is adjustable as a function of amplification factor and is coupled...
US-1,005,0645 Joint encryption and error correction encoding
A technique includes jointly encrypting and error encoding plain text data. The joint encryption and error encoding includes processing plain text data in an...
US-1,005,0644 Receiver, wireless communication system, and wireless communication method
A wireless communication technique in which information that has been encoded and interleaved (the sequence of bits has been rearranged) on the transmission...
US-1,005,0643 Low-density parity-check apparatus and operation method thereof
The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration...
US-1,005,0642 Low power scheme for bit flipping low density parity check decoder
A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the...
US-1,005,0641 List manipulation circuits
Examples disclosed herein relate to very large-scale integration (VLSI) list manipulation circuits. In accordance with some examples disclosed herein, a list...
US-1,005,0640 High speed data weighted averaging architecture
Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current...
US-1,005,0639 Partially asynchronous clock scheme for SAR ADC
A method and apparatus are provided for controlling an SAR ADC by generating a first signal to control sampling of an analog input voltage at a DAC, and then...
US-1,005,0638 Method of gain calibration in a successive approximation register analog-to-digital converter and a successive...
A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN),...
US-1,005,0637 Low-power conversion between analog and digital signals using adjustable feedback filter
A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input...
US-1,005,0636 Methods and apparatus to reduce non-linearity in analog to digital converters
Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to...
US-1,005,0635 Amplifier calibration
A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The...
US-1,005,0634 Quantization noise cancellation for fractional-N phased-locked loop
A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of...
US-1,005,0633 Clock generation circuit, and semiconductor device and system using the same
A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock...
US-1,005,0632 Counter-based SYSREF implementation
A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be...
US-1,005,0631 Systems and methods for synchronizing multiple oscilloscopes
In an exemplary embodiment of the present invention, a master oscilloscope propagates a slave signal to one or more slave oscilloscopes. The slave signal...
US-1,005,0630 Flux-tunable qubit device with multiple Josephson junctions
In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop...
US-1,005,0629 Multi-buffered shift register input matrix to FPGA
A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the...
US-1,005,0628 Field-programmable analog array and field programmable mixed signal array using same
A field-programmable analog array including an array of a plurality of programmable analog timing circuits, the field-programmable analog array being...
US-1,005,0627 Information processing device, PLD management program, and PLD management method
An information processing device includes a processor configured to execute a program; and a programmable circuit device (a PLD hereafter) having a...
US-1,005,0626 CMOS inverter and electronic device using the CMOS inverter
Disclosed is a CMOS inverter, including a first selector, a second selector, and a first transistor, a second transistor, a third transistor and a fourth...
US-1,005,0625 Techniques and devices for level-shifting a signal
Techniques and devices for level-shifting a signal are described. A level-shifting circuit may include an input terminal and components. The input terminal may...
US-1,005,0624 Process-compensated level-up shifter circuit
A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to...
US-1,005,0623 High performance repeater
A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is...
US-1,005,0622 Operating device and appliance having the device
An operating device for an electronic household appliance contains a rotary control knob being mounted on a control panel such that a carrier of the rotary...
US-1,005,0621 Low static current semiconductor device
A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and...
US-1,005,0620 Cascode connected SiC-JFET with SiC-SBD and enhancement device
An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect...
US-1,005,0619 Feedback controller for resonant gate drive
Unique systems, methods, techniques and apparatuses of a gate driver are disclosed herein. One exemplary embodiment is a gate driver comprising a first and...
US-1,005,0618 Reset management circuit and method therefor
A signal management circuit includes a first input terminal to receive a first signal. A first logic portion is coupled to the first input terminal and...
US-1,005,0617 On chip redundant system reset for out of context functional safety SoC
A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented...
US-1,005,0616 Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when...
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices...
US-1,005,0615 Over-voltage protection circuit and associated method
An over-voltage protection circuit for a transistor switch has an error detecting circuit, a dummy load circuit and a driving circuit. The error detecting...
US-1,005,0614 Method and system for reliable bootstrapping switches
Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch...
US-1,005,0613 Phase and amplitude adjustment for sensors
A device includes a micro-electro-mechanical system (MEMS) sensor and a PWM modifier circuitry. The MEMS sensor may include a drive circuitry and a sense...
US-1,005,0612 Resistor-capacitor (RC) delay circuit with a precharge mode
A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the...
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