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Patent # Description
US-1,005,0152 Transistor, semiconductor device, and electronic device
To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor...
US-1,005,0151 Dual-gate TFT array substrate and manufacturing method thereof, and display device
A dual-gate TFT array substrate and manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a common...
US-1,005,0150 Thin-film transistor, method of fabricating thin-film transistor, and display device
A thin-film transistor includes: an oxide semiconductor layer having a channel region, a source region, and a drain region; a gate insulating layer disposed...
US-1,005,0149 Gate structure for semiconductor device
A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop...
US-1,005,0148 Semiconductor device and method of forming the same
A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the...
US-1,005,0147 Semiconductor device and manufacturing method thereof
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which...
US-1,005,0146 Semiconductor device and method of forming the same
A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second...
US-1,005,0145 Methods for forming semiconductor device structures
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed...
US-1,005,0144 Fabrication of a strained region on a substrate
A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the...
US-1,005,0143 Integrated ferroelectric capacitor/ field effect transistor structure
A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate...
US-1,005,0142 Semiconductor device and a method for manufacturing a semiconductor device
The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer,...
US-1,005,0141 Precise control of vertical transistor gate length
A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. Spacers...
US-1,005,0140 Rectifier diode
A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following...
US-1,005,0139 Semiconductor device including a LDMOS transistor and method
In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization...
US-1,005,0138 Nitride semiconductor device
A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate,...
US-1,005,0137 Enhanced normally-off high electron mobility heterojunction transistor
A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type...
US-1,005,0136 High-power and high-frequency heterostructure field-effect transistor
In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source...
US-1,005,0135 Semiconductor device and method for driving same
A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second...
US-1,005,0134 Methods for fabricating anode shorted field stop insulated gate bipolar transistor
A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor...
US-1,005,0133 Application of thin insulating film layer in semiconductor device and method of manufacturing semiconductor device
In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime...
US-1,005,0132 Method for manufacturing semiconductor device
A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved....
US-1,005,0131 Method of forming a polysilicon sidewall oxide region in a memory cell
Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be...
US-1,005,0130 Method of fabricating a semiconductor structure by asymmetric oxidation of fin material formed under gate stack
The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor...
US-1,005,0129 Method of forming fine patterns
A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first...
US-1,005,0128 Gate structure of field effect transistor with footing
In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure...
US-1,005,0127 Array substrate and display panel including the same
An array substrate for a display device is disclosed. The array substrate includes a substrate comprising a plurality of subpixels, at least one of which is a...
US-1,005,0126 Apparatus and method for power MOS transistor
A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second...
US-1,005,0125 Vertical-transport field-effect transistors with an etched-through source/drain cavity
Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor...
US-1,005,0124 Method for producing a pillar-shaped semiconductor device
A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite...
US-1,005,0123 Integrated vertical nanowire memory
A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the...
US-1,005,0122 Semiconductor device and manufacturing method of the same
To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side...
US-1,005,0121 Replacement metal gate structures
Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method...
US-1,005,0119 Method for late differential SOI thinning for improved FDSOI performance and HCI optimization
Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI...
US-1,005,0118 Semiconductor device configured for avoiding electrical shorting
In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second...
US-1,005,0117 Method of forming a high electron mobility transistor
A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer...
US-1,005,0116 Semiconductor device structure and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a...
US-1,005,0115 Tapered gate oxide in LDMOS devices
Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a...
US-1,005,0114 Semiconductor device and method of manufacturing the same
A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein,...
US-1,005,0113 Semiconductor device with needle-shaped field plates and a gate structure with edge and node portions
A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a...
US-1,005,0112 Electron gas confinement heterojunction transistor
A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a...
US-1,005,0111 Semiconductor device channel system and method
A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary...
US-1,005,0110 Device isolation for III-V substrates
Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is...
US-1,005,0109 Silicon carbide semiconductor substrate, method for manufacturing silicon carbide semiconductor substrate, and...
A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made...
US-1,005,0108 Semiconductor device
A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the...
US-1,005,0107 Nanosheet transistors on bulk material
A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting...
US-1,005,0106 Manufacturing method for semiconductor device
A p.sup.+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n.sup.- drift layer and an n.sup.+ field stop layer is...
US-1,005,0105 Semiconductor device
To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by...
US-1,005,0104 Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same
A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first...
US-1,005,0103 Method of forming semiconductor structures including metal insulator metal capacitor
A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a...
US-1,005,0102 Semiconductor device and manufacturing method thereof
Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive...
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