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Patent # Description
US-1,005,0049 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-1,005,0048 Semiconductor memory device and method of manufacturing semiconductor memory device
A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating...
US-1,005,0047 Method to improve floating gate uniformity for non-volatile memory device
The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a...
US-1,005,0046 Static random-access memory (SRAM) cell array and forming method thereof
A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein...
US-1,005,0045 SRAM cell with balanced write port
An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of...
US-1,005,0044 Static random-access memory device
The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading...
US-1,005,0043 Static random access memory (SRAM) using FinFETs with varying widths of fin structures
In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first...
US-1,005,0042 SRAM cell and logic cell design
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell...
US-1,005,0041 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first...
US-1,005,0040 Semiconductor non-volatile DRAM (NVDRAM) device
A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM...
US-1,005,0039 Semiconductor structures with deep trench capacitor and methods of manufacture
An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench...
US-1,005,0038 Semiconductor devices including a gate structure in a substrate
Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device...
US-1,005,0037 Method and circuit for integrated circuit body biasing
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices...
US-1,005,0036 Semiconductor structure having common gate
Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after...
US-1,005,0035 Method of making protective layer over polysilicon structure
A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of...
US-1,005,0034 Semiconductor device and associated methods
A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an ...
US-1,005,0033 High voltage integration for HKMG technology
The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate...
US-1,005,0032 System on chip
Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a...
US-1,005,0031 Power conventer and semiconductor device
A power converter includes a semiconductor element disposed on a substrate, a thermistor element for detecting the temperature of the substrate, the thermistor...
US-1,005,0030 Semiconductor device and fabricating method thereof
A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET...
US-1,005,0029 Semiconductor device
A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection...
US-1,005,0028 Semiconductor device with reduced leakage current
An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair...
US-1,005,0027 Quilt packaging system with mated metal interconnect nodules and voids
First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface...
US-1,005,0026 Display apparatus
A display apparatus includes a light emitting diode part and a thin film (TFT) panel configured to drive the light emitting diode part. The light emitting diode...
US-1,005,0025 Power converter monolithically integrating transistors, carrier, and components
A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110)....
US-1,005,0024 Semiconductor package and manufacturing method of the same
The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged...
US-1,005,0023 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-1,005,0022 Optoelectronic component
An optoelectronic component for mixing electromagnetic radiation having different wavelengths, for example, for the far field is disclosed. In an embodiment the...
US-1,005,0021 Die device, semiconductor device and method for making the same
A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the...
US-1,005,0020 Stack-type semiconductor package
A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a...
US-1,005,0019 Method of manufacturing wafer level package and wafer level package manufactured thereby
Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy...
US-1,005,0018 3DIC structure and methods of forming
A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The...
US-1,005,0017 Semiconductor apparatus and semiconductor system including the same
A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may...
US-1,005,0016 Fan-out semiconductor package
A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component...
US-1,005,0015 Multi-device flexible electronics system on a chip (SOC) process integration
Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be...
US-1,005,0014 Circuit substrate and method of manufacturing same
A circuit substrate of one aspect of the present invention includes a first substrate body made of a flexible wiring substrate and having a first edge and a...
US-1,005,0013 Packaged semiconductor devices and packaging methods
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an...
US-1,005,0012 Method for semiconductor die removal rework
Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized...
US-1,005,0011 Method of manufacturing semiconductor device
Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding...
US-1,005,0010 Selectively cross-linked thermal interface materials
A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to...
US-1,005,0009 Methods and apparatus for improved bonding
Various embodiments of the present technology may comprise a method and apparatus for improved bonding and may operate in conjunction with a main platform...
US-1,005,0008 Method and system for automatic bond arm alignment
A method, as well as a system implementing the method, for automatically aligning a bond arm with respect to a bonding support surface for supporting a...
US-1,005,0007 Electronic device
An electronic device includes: a substrate having an upper surface (front surface) on which a semiconductor chip is mounted, and a lower surface (back surface)...
US-1,005,0006 Chip package and method for forming the same
A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto...
US-1,005,0005 Semiconductor resin composition, semiconductor resin film, and semiconductor device using the same
The objective of the present invention is to obtain a semiconductor resin composition having a sufficiently low coefficient of linear expansion of the cured...
US-1,005,0004 Fully molded peripheral package on package device
A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating...
US-1,005,0003 Elongated pad structure
A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated...
US-1,005,0002 Managing parasitic capacitance and voltage handling of stacked radio frequency devices
Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a...
US-1,005,0001 Packaging device and method of making the same
The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is...
US-1,005,0000 Bump-on-trace structures with high assembly yield
A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace...
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