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Patent # Description
US-1,005,0029 Semiconductor device
A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection...
US-1,005,0028 Semiconductor device with reduced leakage current
An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair...
US-1,005,0027 Quilt packaging system with mated metal interconnect nodules and voids
First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface...
US-1,005,0026 Display apparatus
A display apparatus includes a light emitting diode part and a thin film (TFT) panel configured to drive the light emitting diode part. The light emitting diode...
US-1,005,0025 Power converter monolithically integrating transistors, carrier, and components
A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110)....
US-1,005,0024 Semiconductor package and manufacturing method of the same
The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged...
US-1,005,0023 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-1,005,0022 Optoelectronic component
An optoelectronic component for mixing electromagnetic radiation having different wavelengths, for example, for the far field is disclosed. In an embodiment the...
US-1,005,0021 Die device, semiconductor device and method for making the same
A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the...
US-1,005,0020 Stack-type semiconductor package
A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a...
US-1,005,0019 Method of manufacturing wafer level package and wafer level package manufactured thereby
Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy...
US-1,005,0018 3DIC structure and methods of forming
A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The...
US-1,005,0017 Semiconductor apparatus and semiconductor system including the same
A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may...
US-1,005,0016 Fan-out semiconductor package
A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component...
US-1,005,0015 Multi-device flexible electronics system on a chip (SOC) process integration
Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be...
US-1,005,0014 Circuit substrate and method of manufacturing same
A circuit substrate of one aspect of the present invention includes a first substrate body made of a flexible wiring substrate and having a first edge and a...
US-1,005,0013 Packaged semiconductor devices and packaging methods
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an...
US-1,005,0012 Method for semiconductor die removal rework
Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized...
US-1,005,0011 Method of manufacturing semiconductor device
Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding...
US-1,005,0010 Selectively cross-linked thermal interface materials
A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to...
US-1,005,0009 Methods and apparatus for improved bonding
Various embodiments of the present technology may comprise a method and apparatus for improved bonding and may operate in conjunction with a main platform...
US-1,005,0008 Method and system for automatic bond arm alignment
A method, as well as a system implementing the method, for automatically aligning a bond arm with respect to a bonding support surface for supporting a...
US-1,005,0007 Electronic device
An electronic device includes: a substrate having an upper surface (front surface) on which a semiconductor chip is mounted, and a lower surface (back surface)...
US-1,005,0006 Chip package and method for forming the same
A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto...
US-1,005,0005 Semiconductor resin composition, semiconductor resin film, and semiconductor device using the same
The objective of the present invention is to obtain a semiconductor resin composition having a sufficiently low coefficient of linear expansion of the cured...
US-1,005,0004 Fully molded peripheral package on package device
A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating...
US-1,005,0003 Elongated pad structure
A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated...
US-1,005,0002 Managing parasitic capacitance and voltage handling of stacked radio frequency devices
Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a...
US-1,005,0001 Packaging device and method of making the same
The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is...
US-1,005,0000 Bump-on-trace structures with high assembly yield
A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace...
US-1,004,9999 Electronic device
A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least...
US-1,004,9998 Conductive connections, structures with such connections, and methods of manufacture
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a...
US-1,004,9997 Semiconductor device and method of fabricating the same
A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper...
US-1,004,9996 Surface finishes for high density interconnect architectures
An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include...
US-1,004,9995 Bonding film
A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second...
US-1,004,9994 Contact pads with sidewall spacers and method of making contact pads with sidewall spacers
A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads...
US-1,004,9993 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,004,9992 Ternary PUF unit and circuit realized by CNFET
The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column...
US-1,004,9991 Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit,...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower...
US-1,004,9990 Solder ball protection in packages
An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer...
US-1,004,9989 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes...
US-1,004,9988 Semiconductor device package substrate having a fiducial mark
A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes...
US-1,004,9987 Enhanced fiducial visibility and recognition
Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of...
US-1,004,9986 Package structures and methods of making the same
A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An...
US-1,004,9985 Contact line having insulating spacer therein and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a...
US-1,004,9984 Semiconductor device and method of manufacturing the same
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating...
US-1,004,9983 Semiconductor device and method
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a...
US-1,004,9982 Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower...
US-1,004,9980 Low resistance seed enhancement spacers for voidless interconnect structures
An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier...
US-1,004,9979 IC structure including TSV having metal resistant to high temperatures and method of forming same
An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a...
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