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Patent # Description
US-1,004,9999 Electronic device
A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least...
US-1,004,9998 Conductive connections, structures with such connections, and methods of manufacture
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a...
US-1,004,9997 Semiconductor device and method of fabricating the same
A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper...
US-1,004,9996 Surface finishes for high density interconnect architectures
An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include...
US-1,004,9995 Bonding film
A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second...
US-1,004,9994 Contact pads with sidewall spacers and method of making contact pads with sidewall spacers
A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads...
US-1,004,9993 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,004,9992 Ternary PUF unit and circuit realized by CNFET
The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column...
US-1,004,9991 Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit,...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower...
US-1,004,9990 Solder ball protection in packages
An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer...
US-1,004,9989 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes...
US-1,004,9988 Semiconductor device package substrate having a fiducial mark
A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes...
US-1,004,9987 Enhanced fiducial visibility and recognition
Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of...
US-1,004,9986 Package structures and methods of making the same
A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An...
US-1,004,9985 Contact line having insulating spacer therein and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a...
US-1,004,9984 Semiconductor device and method of manufacturing the same
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating...
US-1,004,9983 Semiconductor device and method
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a...
US-1,004,9982 Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower...
US-1,004,9981 Through via structure, semiconductor device and manufacturing method thereof
A through via structure includes a semiconductor substrate, an underlying insulation layer, a conductive via and a sidewall insulation layer. The underlying...
US-1,004,9980 Low resistance seed enhancement spacers for voidless interconnect structures
An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier...
US-1,004,9979 IC structure including TSV having metal resistant to high temperatures and method of forming same
An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a...
US-1,004,9978 Semiconductor module
A semiconductor module includes a wiring substrate and two semiconductor devices mounted on the wiring substrate. The semiconductor module includes a housing...
US-1,004,9977 Semiconductor package on package structure and method of forming the same
A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and...
US-1,004,9976 Semiconductor substrate and manufacturing method thereof
A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit...
US-1,004,9975 Substrate structure
A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the...
US-1,004,9974 Metal silicate spacers for fully aligned vias
A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or...
US-1,004,9973 Electronic package and fabrication method thereof and substrate structure
A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the...
US-1,004,9972 Wiring board, electronic component device, method for manufacturing wiring board, and method for manufacturing...
A wiring board includes a first wiring layer, an insulating layer, and a pad. The insulating layer is formed on the first wiring layer. The pad is formed on the...
US-1,004,9971 Package structure to enhance yield of TMI interconnections
An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound...
US-1,004,9970 Methods of manufacturing printed circuit board and semiconductor package
A method of manufacturing a semiconductor package according to the present inventive concepts comprises preparing a printed circuit board (PCB) including a...
US-1,004,9969 Integrated circuit
An integrated circuit includes a lead frame having a die attach paddle with a slot extending through the die attach paddle from a first surface to a second...
US-1,004,9968 Semiconductor device
To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode...
US-1,004,9967 Method of producing an optoelectronic component and optoelectronic component
A method of producing an optoelectronic component includes providing a lead frame having an upper side including a contact region and a chip reception region...
US-1,004,9966 Semiconductor device and corresponding method
A semiconductor device includes a leadframe that includes contact pins and a semiconductor die that has protruding connection formations. A flexible support...
US-1,004,9965 Through-substrate vias and methods for forming the same
A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the...
US-1,004,9964 Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first...
US-1,004,9963 Power electronics module
A power electronics module is provided having one or more power converter semiconductor components. The power electronics module further has a substrate having...
US-1,004,9962 Arrangement of multiple power semiconductor chips and method of manufacturing the same
A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power...
US-1,004,9961 Partially molded direct chip attach package structures for connectivity module solutions
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a...
US-1,004,9960 Semiconductor device
According to the present invention, a grease layer having a grease as a constituent material is provided in a filling region lying between a heat dissipation...
US-1,004,9959 Thermal interface pad material with perforated liner
This invention relates to a thermal interface device (206) arranged to provide a thermal coupling interface between a heat-generating unit (202) and a...
US-1,004,9958 Semiconductor device
A semiconductor device includes a semiconductor module and a cooler. The semiconductor device includes semiconductor element(s) within a molded resin and a heat...
US-1,004,9957 On-chip control of thermal cycling
A method, system, and computer program product for on-chip control of thermal cycling in an integrated circuit (IC) are provided in the illustrative...
US-1,004,9956 Passivation structure and method of making the same
A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric...
US-1,004,9955 Fabrication method of wafer level packaging semiconductor package with sandwich structure of support plate...
A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the...
US-1,004,9954 Semiconductor package having routable encapsulated conductive substrate and method
A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame...
US-1,004,9953 Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate...
A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die....
US-1,004,9952 Method of fabricating a semiconductor module with a inclined groove formed in resin side surface
A manufacturing method of a semiconductor module includes: sealing an assembly with resin, the assembly including a semiconductor chip, a heat-dissipation plate...
US-1,004,9951 Bonded substrate, method for manufacturing the same, and support substrate for bonding
A method for manufacturing a bonded substrate is provided, the bonded substrate including a single-crystal semiconductor substrate on a sintered-body substrate...
US-1,004,9950 Multi-layer substrate for semiconductor packaging
The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a...
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