Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-1,004,9949 |
In-situ packaging decapsulation feature for electrical fault localization An IR camera is used to image an IC to identify hot spots. The objective of the IR camera is removed and laser optics are inserted into the optical axis of the... |
| US-1,004,9948 |
Power switching system for ESC with array of thermal control elements A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control... |
| US-1,004,9947 |
Method of manufacturing a substrate A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially... |
| US-1,004,9946 |
Vertical CMOS structure and method A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that... |
| US-1,004,9945 |
Forming a CMOS with dual strained channels The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and... |
| US-1,004,9944 |
Method of manufacturing selective nanostructures into finFET process flow A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and... |
| US-1,004,9943 |
Methods of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation... |
| US-1,004,9942 |
Asymmetric semiconductor device and method of forming same An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped... |
| US-1,004,9941 |
Semiconductor isolation structure with air gaps in deep trenches A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor... |
| US-1,004,9940 |
Structure and method for metal gates with roughened barrier layer A method of forming a semiconductor device includes receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the... |
| US-1,004,9939 |
Semiconductor device and a method for fabricating the same In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of... |
| US-1,004,9938 |
Semiconductor devices, FinFET devices, and manufacturing methods thereof Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a... |
| US-1,004,9936 |
Semiconductor device having merged epitaxial features with Arc-like bottom
surface and method of making the same A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate,... |
| US-1,004,9935 |
Integrated circuit package having pin up interconnect An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an... |
| US-1,004,9934 |
Wafer processing method A wafer processing method divides a wafer into individual device chips along division lines. The method includes attaching an adhesive tape to the front side of... |
| US-1,004,9933 |
Element chip manufacturing method An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second... |
| US-1,004,9932 |
Method of manufacturing of a sidewall opening of an interconnect of a
semiconductor device A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An... |
| US-1,004,9931 |
Method of manufacturing a semiconductor device including through silicon
plugs A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive... |
| US-1,004,9930 |
Memory device and operation method thereof A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a... |
| US-1,004,9929 |
Method of making semiconductor structure having contact plug The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first... |
| US-1,004,9928 |
Embedded 3D interposer structure A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs)... |
| US-1,004,9927 |
Seam-healing method upon supra-atmospheric process in diffusion promoting
ambient Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the... |
| US-1,004,9926 |
Metal lines having etch-bias independent height A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level... |
| US-1,004,9925 |
Metal-semiconductor contact structure with doped interlayer Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of... |
| US-1,004,9924 |
Selective formation of metallic films on metallic surfaces Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic... |
| US-1,004,9922 |
Method of forming trenches A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a... |
| US-1,004,9921 |
Method for selectively sealing ultra low-k porous dielectric layer using
flowable dielectric film formed from... Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods... |
| US-1,004,9920 |
Reduced tip-to-tip and via pitch at line end A semiconductor structure and methods of forming the semiconductor structure forming a single damascene line formed of a conductive material in a dielectric... |
| US-1,004,9919 |
Semiconductor device including a target integrated circuit pattern A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the... |
| US-1,004,9918 |
Directional patterning methods Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a... |
| US-1,004,9917 |
FDSOI channel control by implanted high-K buried oxide Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are... |
| US-1,004,9916 |
Method of manufacturing a germanium-on-insulator substrate A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second... |
| US-1,004,9915 |
Three dimensional integrated circuit A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the... |
| US-1,004,9914 |
Method for thinning substrates According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried... |
| US-1,004,9913 |
Methods for SiO.sub.2 filling of fine recessed features and selective
SiO.sub.2 deposition on catalytic surfaces Methods for void-free SiO.sub.2 filling of fine recessed features and selective SiO.sub.2 deposition on catalytic surfaces are described. According to one... |
| US-1,004,9912 |
Method of manufacturing a semiconductor device having a vertical edge
termination structure A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame... |
| US-1,004,9911 |
Temporally pulsed and kinetically modulated CVD dielectrics for gapfill
applications A method for performing temporally pulsed chemical vapor deposition (CVD) is provided, including: providing a first reactant configured to adsorb on exposed... |
| US-1,004,9910 |
Manufacturing method of semiconductor device and semiconductor
manufacturing apparatus using a conveying robot... An object of the present invention is to prevent a semiconductor substrate from being damaged when the substrate is conveyed by a conveying robot provided in a... |
| US-1,004,9909 |
Wafer handler and methods of manufacture A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed... |
| US-1,004,9908 |
Methods and apparatus for electrostatic chuck repair and refurbishment In one embodiment of the invention, a substrate support assembly comprises an electrostatic chuck having an electrode embedded therein and having an aperture... |
| US-1,004,9907 |
Automated module for assembly lines and method to actuate and control
thereof An automated module for assembly lines to assemble electronic devices includes a plurality of cells. Each cell includes a support structure, a control unit and... |
| US-1,004,9906 |
Substrate processing apparatus Provided is a substrate processing apparatus, which comprises a processing chamber, a substrate sensing assembly, a rotation shaft and a driving assembly. A... |
| US-1,004,9905 |
Substrate heat treatment apparatus, substrate heat treatment method,
storage medium and... A substrate heat treatment apparatus includes: a placement unit on which a substrate is placed; a heat treatment unit for heating or cooling the substrate on... |
| US-1,004,9904 |
Method and system for moving a substrate A method and a system for moving a substrate, the system includes a chamber, a chuck, a movement system that is positioned outside the chamber, a controller, an... |
| US-1,004,9903 |
Method of manufacturing a high definition heater system Methods of manufacturing a heater are provided that generally include forming a laminate having a dielectric layer, a first double-sided adhesive dielectric... |
| US-1,004,9902 |
Substrate stack holder, container and method for parting a substrate stack A substrate stack holder, a container comprising a plurality of substrate stack holders, and a method for parting a substrate stack. The substrate stack holder... |
| US-1,004,9901 |
Apparatus and method for wafer level bonding A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by... |
| US-1,004,9900 |
Substrate treatment method A substrate treatment method and apparatus including a change controlling unit which changes at least one of a protection liquid application position relative... |
| US-1,004,9899 |
Substrate cleaning apparatus A substrate cleaning apparatus for removing particles adhered to a substrate includes a cleaning chamber for cleaning a substrate under a vacuum atmosphere, a... |
| US-1,004,9898 |
Semiconductor device packages, packaging methods, and packaged
semiconductor devices Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.