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| Patent # | Description |
|---|---|
| US-1,004,9927 |
Seam-healing method upon supra-atmospheric process in diffusion promoting
ambient Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the... |
| US-1,004,9926 |
Metal lines having etch-bias independent height A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level... |
| US-1,004,9925 |
Metal-semiconductor contact structure with doped interlayer Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of... |
| US-1,004,9924 |
Selective formation of metallic films on metallic surfaces Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic... |
| US-1,004,9922 |
Method of forming trenches A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a... |
| US-1,004,9921 |
Method for selectively sealing ultra low-k porous dielectric layer using
flowable dielectric film formed from... Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods... |
| US-1,004,9920 |
Reduced tip-to-tip and via pitch at line end A semiconductor structure and methods of forming the semiconductor structure forming a single damascene line formed of a conductive material in a dielectric... |
| US-1,004,9919 |
Semiconductor device including a target integrated circuit pattern A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the... |
| US-1,004,9918 |
Directional patterning methods Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a... |
| US-1,004,9917 |
FDSOI channel control by implanted high-K buried oxide Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are... |
| US-1,004,9916 |
Method of manufacturing a germanium-on-insulator substrate A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second... |
| US-1,004,9915 |
Three dimensional integrated circuit A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the... |
| US-1,004,9914 |
Method for thinning substrates According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried... |
| US-1,004,9913 |
Methods for SiO.sub.2 filling of fine recessed features and selective
SiO.sub.2 deposition on catalytic surfaces Methods for void-free SiO.sub.2 filling of fine recessed features and selective SiO.sub.2 deposition on catalytic surfaces are described. According to one... |
| US-1,004,9912 |
Method of manufacturing a semiconductor device having a vertical edge
termination structure A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame... |
| US-1,004,9911 |
Temporally pulsed and kinetically modulated CVD dielectrics for gapfill
applications A method for performing temporally pulsed chemical vapor deposition (CVD) is provided, including: providing a first reactant configured to adsorb on exposed... |
| US-1,004,9910 |
Manufacturing method of semiconductor device and semiconductor
manufacturing apparatus using a conveying robot... An object of the present invention is to prevent a semiconductor substrate from being damaged when the substrate is conveyed by a conveying robot provided in a... |
| US-1,004,9909 |
Wafer handler and methods of manufacture A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed... |
| US-1,004,9908 |
Methods and apparatus for electrostatic chuck repair and refurbishment In one embodiment of the invention, a substrate support assembly comprises an electrostatic chuck having an electrode embedded therein and having an aperture... |
| US-1,004,9907 |
Automated module for assembly lines and method to actuate and control
thereof An automated module for assembly lines to assemble electronic devices includes a plurality of cells. Each cell includes a support structure, a control unit and... |
| US-1,004,9906 |
Substrate processing apparatus Provided is a substrate processing apparatus, which comprises a processing chamber, a substrate sensing assembly, a rotation shaft and a driving assembly. A... |
| US-1,004,9905 |
Substrate heat treatment apparatus, substrate heat treatment method,
storage medium and... A substrate heat treatment apparatus includes: a placement unit on which a substrate is placed; a heat treatment unit for heating or cooling the substrate on... |
| US-1,004,9904 |
Method and system for moving a substrate A method and a system for moving a substrate, the system includes a chamber, a chuck, a movement system that is positioned outside the chamber, a controller, an... |
| US-1,004,9903 |
Method of manufacturing a high definition heater system Methods of manufacturing a heater are provided that generally include forming a laminate having a dielectric layer, a first double-sided adhesive dielectric... |
| US-1,004,9902 |
Substrate stack holder, container and method for parting a substrate stack A substrate stack holder, a container comprising a plurality of substrate stack holders, and a method for parting a substrate stack. The substrate stack holder... |
| US-1,004,9901 |
Apparatus and method for wafer level bonding A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by... |
| US-1,004,9900 |
Substrate treatment method A substrate treatment method and apparatus including a change controlling unit which changes at least one of a protection liquid application position relative... |
| US-1,004,9899 |
Substrate cleaning apparatus A substrate cleaning apparatus for removing particles adhered to a substrate includes a cleaning chamber for cleaning a substrate under a vacuum atmosphere, a... |
| US-1,004,9898 |
Semiconductor device packages, packaging methods, and packaged
semiconductor devices Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device... |
| US-1,004,9897 |
Extrusion-resistant solder interconnect structures and methods of forming Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure... |
| US-1,004,9896 |
Lid attach optimization to limit electronic package warpage An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and... |
| US-1,004,9895 |
Thermal block assemblies and instruments providing low thermal
non-uniformity for rapid thermal cycling The present teachings disclose various embodiments of a thermal block assembly having low thermal non-uniformity throughout the thermal block assembly.... |
| US-1,004,9894 |
Package structures and methods for forming the same A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally... |
| US-1,004,9893 |
Semiconductor device with a conductive post A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first... |
| US-1,004,9892 |
Method for processing photoresist materials and structures Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques... |
| US-1,004,9891 |
Selective in situ cobalt residue removal Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing... |
| US-1,004,9890 |
Semiconductor structure and method of manufacturing the same The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed... |
| US-1,004,9888 |
System and method for regenerating phosphoric acid solution, and apparatus
and method for treating substrate Disclosed is a method of regenerating a phosphoric acid solution from a treatment liquid including silicon (Si), hydrogen fluoride (HF), and phosphoric acid,... |
| US-1,004,9887 |
Method of planarizing substrate surface A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material... |
| US-1,004,9886 |
System and method for damage reduction in light-assisted processes A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the... |
| US-1,004,9885 |
Method for patterning a plurality of features for fin-like field-effect
transistor (FinFET) devices A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask... |
| US-1,004,9884 |
Anodic etching of substrates A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a... |
| US-1,004,9883 |
MRAM dry etching residue removal composition, method of producing
magnetoresistive random access memory, and... An object is to provide an MRAM dry etching residue removal composition capable of removing dry etching residues while suppressing damage to a substrate... |
| US-1,004,9882 |
Method for fabricating semiconductor device including forming a dielectric
layer on a structure having a height... A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on... |
| US-1,004,9881 |
Method and apparatus for selective nitridation process Embodiments of the invention provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a remote plasma system... |
| US-1,004,9880 |
Semiconductor device and method of manufacturing semiconductor device A method of manufacturing a semiconductor device, where the device includes a donor layer that is obtained by changing a crystal defect formed in a... |
| US-1,004,9879 |
Self aligned silicon carbide contact formation using protective layer A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer... |
| US-1,004,9878 |
Self-aligned patterning process Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method... |
| US-1,004,9877 |
Patterning method A method for forming fine patterns is described. A bottom layer, a hard mask layer, a buffer mask layer and a mask layer are sequentially formed on a substrate.... |
| US-1,004,9876 |
Removal of trilayer resist without damage to underlying structure A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The... |
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