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Patent # Description
US-1,004,9773 Heating plasma for fusion power using neutral beam injection
In one embodiment, a fusion reactor includes two internal magnetic coils suspended within an enclosure, a center magnetic coil coaxial with the two internal...
US-1,004,9772 System and method for creation, operation and use of a clinical research database
In a method, a user at a client device may be provided with a user interface having user interactive controls, including a control to enable selection from...
US-1,004,9771 Laplacian and Tikhonov regularization for voltage mapping with a medical device
An embodiment of a method for solving the inverse problem of electrophysiology and determining a voltage distribution on a surface of a tissue may comprise...
US-1,004,9770 Prediction of recurrence of non-small cell lung cancer
Methods, apparatus, and other embodiments associated with predicting non-small cell lung cancer (NSCLC) patient response to adjuvant chemotherapy therapy using...
US-1,004,9769 Clinical component routing system
One or more techniques and/or systems are disclosed for a system that may be used for managing routing of clinical operation component lines. A first...
US-1,004,9768 Programmable insulin pump
An apparatus for delivering a bolus of a medical agent to a patient. The apparatus comprises a pump mechanism, a data input device, and a processor in data...
US-1,004,9767 Test panel to measure blood neurotoxin levels in prematernal women and for the general public in relation to...
A prescribed diagnostic blood test panel is directed to countering autistic and mentally affected births and assessing the continued healthy mental state of the...
US-1,004,9766 Method and apparatus for secure setup of clinical trial client device
A method, device and system for transceiving clinical trial related information includes a client device and a server that communicate. An application of the...
US-1,004,9765 Dynamic random access memory having e-fuses used as capacitors coupled to latches
A dynamic random access memory (DRAM) has a main memory cell array and a redundant component unit. The redundant component unit includes a plurality of e-fuses...
US-1,004,9764 Control method for memory device and memory controller
A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a...
US-1,004,9763 Semiconductor memory apparatus
A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit...
US-1,004,9762 Shift register unit, operation method therefor and shift register
Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an...
US-1,004,9761 Magnetic element, skyrmion memory, solid-state electronic device, data-storage device, data processing and...
To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element...
US-1,004,9760 Programming and verification methods for three-dimensional memory device
According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a...
US-1,004,9759 Reducing verification checks when programming a memory device
Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to...
US-1,004,9758 Word line dependent pass voltages in non-volatile memory
Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile...
US-1,004,9757 Techniques for dynamically determining performance of read reclaim operations
Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read...
US-1,004,9756 Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data...
A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The...
US-1,004,9755 Storage device including nonvolatile memory device and controller with varied read weights
A storage device includes a nonvolatile memory device and a controller. The nonvolatile memory device includes multiple memory blocks, each of which includes...
US-1,004,9754 Controller and operating method thereof
An operating method of a controller includes: searching, by using a predetermined read voltage, a valid word line coupled to a memory cell having a...
US-1,004,9753 Reconfigurable sense amplifier
A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its...
US-1,004,9752 Method and apparatus for process corner compensation for memory state sensing
In one embodiment, an apparatus comprises a memory array; a sense circuit comprising a first transistor and a sense node coupled to the first transistor and...
US-1,004,9751 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a plurality of data latches; and an inverter shared by the plurality of data latches. The...
US-1,004,9750 Methods including establishing a negative body potential in a memory cell
Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation...
US-1,004,9749 Two-level and multi-level data storage semiconductor memory device
A semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural...
US-1,004,9748 Semiconductor memory device and method for program operation having program loops by step voltage
Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory...
US-1,004,9747 NAND flash memory and program method thereof for suppressing influence of floating gate coupling
A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method...
US-1,004,9746 Memory device and operating method including a partial program operation and a partial erase operation thereof
There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The...
US-1,004,9745 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control...
US-1,004,9744 Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same
Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may...
US-1,004,9743 Semiconductor device and method of manufacturing the same
A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. The semiconductor device may...
US-1,004,9742 Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
A shared floating gate device, the device including an nFET including an nFET gate dielectric, a pFET including a pFET gate dielectric, and a floating gate,...
US-1,004,9741 Non-volatile memory with floating gate having protruding portion
A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the...
US-1,004,9740 Memory circuit with a bistable circuit and a non-volatile element
A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a...
US-1,004,9739 Latching device and method
According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus...
US-1,004,9738 Temperature gradients for controlling memristor switching
A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament...
US-1,004,9737 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-1,004,9736 Memory device including decoder for a program pulse and related methods
An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes...
US-1,004,9735 Method, system and device for complementary non-volatile memory device operation
Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in...
US-1,004,9733 Reusing sneak current in accessing memory cells
A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with...
US-1,004,9732 Determining a state of memristors in a crossbar array
In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias...
US-1,004,9731 Periodic refresh of a memory area of a non-volatile memory unit using refresh triggers
A method for carrying out a refresh of a memory area of a non-volatile memory unit of an embedded system includes refreshing the memory area when a...
US-1,004,9730 Crossbar arrays with shared drivers
A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers,...
US-1,004,9729 Flexible memory assistance scheme
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a...
US-1,004,9728 Semiconductor memory device having bit cells
A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second...
US-1,004,9727 Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on...
A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply...
US-1,004,9726 Contention-free dynamic logic
A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The...
US-1,004,9725 Write assist for memories with resistive bit lines
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective...
US-1,004,9724 Aging tolerant register file
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a...
US-1,004,9723 Semiconductor storage device
A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory...
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