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Patent # Description
US-1,004,9746 Memory device and operating method including a partial program operation and a partial erase operation thereof
There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The...
US-1,004,9745 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control...
US-1,004,9744 Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same
Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may...
US-1,004,9743 Semiconductor device and method of manufacturing the same
A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. The semiconductor device may...
US-1,004,9742 Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
A shared floating gate device, the device including an nFET including an nFET gate dielectric, a pFET including a pFET gate dielectric, and a floating gate,...
US-1,004,9741 Non-volatile memory with floating gate having protruding portion
A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the...
US-1,004,9740 Memory circuit with a bistable circuit and a non-volatile element
A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a...
US-1,004,9739 Latching device and method
According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus...
US-1,004,9738 Temperature gradients for controlling memristor switching
A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament...
US-1,004,9737 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-1,004,9736 Memory device including decoder for a program pulse and related methods
An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes...
US-1,004,9735 Method, system and device for complementary non-volatile memory device operation
Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in...
US-1,004,9734 Data storing method of non-volatile memory device by assigning an initial state to data
A data storing method comprises preparing a non-volatile memory device that includes a memory cell array including a plurality of memory cells, wherein the...
US-1,004,9733 Reusing sneak current in accessing memory cells
A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with...
US-1,004,9732 Determining a state of memristors in a crossbar array
In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias...
US-1,004,9731 Periodic refresh of a memory area of a non-volatile memory unit using refresh triggers
A method for carrying out a refresh of a memory area of a non-volatile memory unit of an embedded system includes refreshing the memory area when a...
US-1,004,9730 Crossbar arrays with shared drivers
A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers,...
US-1,004,9729 Flexible memory assistance scheme
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a...
US-1,004,9728 Semiconductor memory device having bit cells
A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second...
US-1,004,9727 Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on...
A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply...
US-1,004,9726 Contention-free dynamic logic
A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The...
US-1,004,9725 Write assist for memories with resistive bit lines
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective...
US-1,004,9724 Aging tolerant register file
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a...
US-1,004,9723 Semiconductor storage device
A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory...
US-1,004,9722 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-1,004,9721 Apparatuses and methods for in-memory operations
The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of...
US-1,004,9720 Dynamic random access memory (DRAM)
According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second...
US-1,004,9719 Voltage system and method for operating the same
The present disclosure provides a voltage system of a DRAM and a method for operating the same. The voltage system includes a first regulator, a second...
US-1,004,9718 Refresh control circuit and memory device including same
A memory device may include: at least one memory bank; and a control circuit suitable for: refreshing the at least one memory bank through a first refresh...
US-1,004,9717 Wear leveling for storage or memory device
A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be...
US-1,004,9716 Refresh request queuing circuitry
An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of...
US-1,004,9715 Semiconductor storage device and method for writing of the same
A semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver....
US-1,004,9714 DRAM and method for managing power thereof
The present disclosure provides a DRAM. The DRAM includes a memory array of memory cells, a control device and a charge pump circuit. The control device derives...
US-1,004,9713 Full bias sensing in a memory array
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be...
US-1,004,9712 Semiconductor device including volatile and non-volatile memory
A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type...
US-1,004,9711 Magnetoresistive memory device
According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements...
US-1,004,9710 Magnetic article and rotation of magnetic spins via spin-orbit effect in same
A nonvolatile memory cell includes: a first fixed magnetic layer; a first nonmagnetic electrode disposed on the first magnetic layer; a memory storage layer...
US-1,004,9709 Port modes for use with memory
Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include...
US-1,004,9708 Semiconductor device and semiconductor system
A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to...
US-1,004,9707 Shifting data
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus...
US-1,004,9706 Memory and method of operating the same
A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection...
US-1,004,9705 Memories having select devices between access lines and in memory cells formed of a same type of circuit element
Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of...
US-1,004,9704 Methods and systems of dynamically managing content for use by a media playback device
Some embodiments provide systems and/or methods of managing content in providing a playback experience associated with a portable storage medium by detecting...
US-1,004,9703 Data reproduction apparatus, control method for data reproduction apparatus, and recording medium storing...
A data reproduction apparatus includes a display, a touch panel, a recording unit, an output unit, a display control unit, and an output controller. The output...
US-1,004,9702 Digital video recorder options for editing content
A system for providing digital video recorder options for editing content is disclosed. In particular, the system may include receiving requests for a first...
US-1,004,9701 Video editing apparatus, video editing method, and non-transitory computer readable medium
A video editing apparatus includes a storing unit, an input unit, a segment selection unit, and a generation unit. The storing unit stores video data along with...
US-1,004,9700 Display apparatus and control method thereof
A display apparatus including a display unit, adapted to playback a sequence of images, comprises: a detection configured to detect an attitude of the display...
US-1,004,9699 Disc tray and tray holder
A disc tray includes a bottom wall including an outer periphery and an inner rib supporter supporting the lowermost disc from below. The bottom wall is...
US-1,004,9698 Interlaced magnetic recording super parity
A storage device includes a storage medium having a plurality of data tracks. At least one data track of the plurality of data tracks includes a number of super...
US-1,004,9697 Write-once storage medium capable of recording data blocks on both land and groove of spiral track
An information recording method of the present disclosure is an information recording method for recording information on a write-once information recording...
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