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Patent # Description
US-1,005,6398 Method of forming split-gate, twin-bit non-volatile memory cell
A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and...
US-1,005,6397 Integrated circuit and method for manufacturing thereof
A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two...
US-1,005,6396 Method of manufacturing semiconductor device and semiconductor device
A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a...
US-1,005,6395 Method of improving localized wafer shape changes
A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a...
US-1,005,6394 Ferroelectric tunnel junction and method of fabrication thereof
A method for fabricating a ferroelectric tunnel junction, comprising growing a hafnium zirconium oxide film barrier layer by sputtering in the presence of...
US-1,005,6393 Application of antiferroelectric like materials in non-volatile memory devices
Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced...
US-1,005,6392 Performing horological functions in commercial transactions using time cells
Mechanisms for controlling a commercial transaction is presented. An article of manufacture has a time cell that is read by an electronic apparatus. In response...
US-1,005,6391 Vertically stacked FinFET fuse
A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced...
US-1,005,6390 FinFET SRAM having discontinuous PMOS fin lines
An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of...
US-1,005,6389 Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or...
US-1,005,6388 Method for fabricating semiconductor device
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the...
US-1,005,6387 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The...
US-1,005,6386 Memory cells and memory arrays
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first...
US-1,005,6385 Semiconductor device including write access transistor whose oxide semiconductor layer including channel...
Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory...
US-1,005,6384 Multi-die fine grain integrated voltage regulation
A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more...
US-1,005,6383 Enhanced channel strain to reduce contact resistance in NMOS FET devices
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor...
US-1,005,6382 Modulating transistor performance
A method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin. The...
US-1,005,6381 Punchthrough stop layers for fin-type field-effect transistors
Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first...
US-1,005,6380 Non-planar semiconductor device having doped sub-fin region and method to fabricate same
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are...
US-1,005,6379 Low voltage (power) junction FET with all-around junction gate
A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region...
US-1,005,6378 Silicon nitride fill for PC gap regions to increase cell density
A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the...
US-1,005,6377 Metal layer routing level for vertical FET SRAM and logic cell scaling
Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of...
US-1,005,6376 Ferroelectric FinFET
A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor...
US-1,005,6375 Semiconductor device and method for fabricating the same
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate...
US-1,005,6374 Switching device
A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating...
US-1,005,6373 Transistor contacts self-aligned in two dimensions
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are...
US-1,005,6372 Double-base-connected bipolar transistors with passive components preventing accidental turn-on
The present application discloses new approaches to providing "passive-off" protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC...
US-1,005,6371 Memory structure having array-under-periphery structure
A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the array...
US-1,005,6370 Semiconductor device
In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor...
US-1,005,6369 Semiconductor device including buried capacitive structures and a method of forming the same
A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a...
US-1,005,6368 Fin diode with increased junction area
A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of...
US-1,005,6367 Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
US-1,005,6366 Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
US-1,005,6365 Semiconductor device
A semiconductor device incudes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain...
US-1,005,6364 Electronic device with adjustable reverse breakdown voltage
An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped...
US-1,005,6363 Methods and systems to improve yield in multiple chips integration processes
The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some...
US-1,005,6362 Multi-phase power converter with common connections
In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises...
US-1,005,6361 Lighting device including a thermally conductive body and a semiconductor light emitting device
A lighting device including a body (10). The body (10) includes a mounting area (11) with a plurality of conductive pads (50, 52) and an elongate member (16)...
US-1,005,6360 Localized redistribution layer structure for embedded component package and method
An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active...
US-1,005,6359 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-1,005,6358 Light-emitting module
Provided is a light-emitting module that achieves high brightness, whose electrode structure is simple and whose brightness distribution has rotational...
US-1,005,6357 Semiconductor light emitting device
A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked...
US-1,005,6356 Chip package circuit board module
A chip package circuit board module includes a circuit board and an original chip. The circuit board includes a first pad and a second pad disposed besides the...
US-1,005,6355 Common-source packaging structure
A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a...
US-1,005,6354 Multi-chip semiconductor apparatus
A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes:...
US-1,005,6353 3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed...
US-1,005,6352 High density chip-to-chip connection
An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads...
US-1,005,6351 Fan-out stacked system in package (SIP) and the methods of making the same
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a...
US-1,005,6350 Fan-out package structure, and manufacturing method thereof
The method of fabricating a fan-out package structure comprises: S1, providing a substrate (1), forming an adhesive layer (2) on the substrate's upper surface;...
US-1,005,6349 Manufacturing method of semiconductor device and semiconductor device thereof
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
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