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Patent # Description
US-1,005,6380 Non-planar semiconductor device having doped sub-fin region and method to fabricate same
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are...
US-1,005,6379 Low voltage (power) junction FET with all-around junction gate
A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region...
US-1,005,6378 Silicon nitride fill for PC gap regions to increase cell density
A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the...
US-1,005,6377 Metal layer routing level for vertical FET SRAM and logic cell scaling
Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of...
US-1,005,6376 Ferroelectric FinFET
A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor...
US-1,005,6375 Semiconductor device and method for fabricating the same
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate...
US-1,005,6374 Switching device
A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating...
US-1,005,6373 Transistor contacts self-aligned in two dimensions
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are...
US-1,005,6372 Double-base-connected bipolar transistors with passive components preventing accidental turn-on
The present application discloses new approaches to providing "passive-off" protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC...
US-1,005,6371 Memory structure having array-under-periphery structure
A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the array...
US-1,005,6370 Semiconductor device
In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor...
US-1,005,6369 Semiconductor device including buried capacitive structures and a method of forming the same
A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a...
US-1,005,6368 Fin diode with increased junction area
A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of...
US-1,005,6367 Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
US-1,005,6366 Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
US-1,005,6365 Semiconductor device
A semiconductor device incudes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain...
US-1,005,6364 Electronic device with adjustable reverse breakdown voltage
An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped...
US-1,005,6363 Methods and systems to improve yield in multiple chips integration processes
The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some...
US-1,005,6362 Multi-phase power converter with common connections
In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises...
US-1,005,6361 Lighting device including a thermally conductive body and a semiconductor light emitting device
A lighting device including a body (10). The body (10) includes a mounting area (11) with a plurality of conductive pads (50, 52) and an elongate member (16)...
US-1,005,6360 Localized redistribution layer structure for embedded component package and method
An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active...
US-1,005,6359 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-1,005,6358 Light-emitting module
Provided is a light-emitting module that achieves high brightness, whose electrode structure is simple and whose brightness distribution has rotational...
US-1,005,6357 Semiconductor light emitting device
A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked...
US-1,005,6356 Chip package circuit board module
A chip package circuit board module includes a circuit board and an original chip. The circuit board includes a first pad and a second pad disposed besides the...
US-1,005,6355 Common-source packaging structure
A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a...
US-1,005,6354 Multi-chip semiconductor apparatus
A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes:...
US-1,005,6353 3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed...
US-1,005,6352 High density chip-to-chip connection
An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads...
US-1,005,6351 Fan-out stacked system in package (SIP) and the methods of making the same
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a...
US-1,005,6350 Fan-out package structure, and manufacturing method thereof
The method of fabricating a fan-out package structure comprises: S1, providing a substrate (1), forming an adhesive layer (2) on the substrate's upper surface;...
US-1,005,6349 Manufacturing method of semiconductor device and semiconductor device thereof
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
US-1,005,6348 Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip...
US-1,005,6347 Bump structure for yield improvement
A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and...
US-1,005,6346 Chip attach frame
A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges...
US-1,005,6345 Conical-shaped or tier-shaped pillar connections
A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical...
US-1,005,6344 Semiconductor device
A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed and...
US-1,005,6343 Packaged semiconductor device with interior polygonal pads
Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure...
US-1,005,6342 Electronic component and electronic device
A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer...
US-1,005,6341 Electronic device with microfilm antenna and related methods
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
US-1,005,6340 Flexible electronic circuit and method for manufacturing same
An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered...
US-1,005,6339 Semiconductor devices
A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer...
US-1,005,6338 Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor...
US-1,005,6337 Thin 3D die with electromagnetic radiation blocking encapsulation
After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the...
US-1,005,6336 Semiconductor device and a method of manufacturing the same
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark....
US-1,005,6335 Prototyping of electronic circuits with edge interconnects
In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities...
US-1,005,6334 Dual metal-insulator-semiconductor contact structure and formulation method
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain...
US-1,005,6333 Stacked multilayer structure and manufacturing method thereof
A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers...
US-1,005,6332 Electronic device with delamination resistant wiring board
This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at...
US-1,005,6331 Programmable via devices with metal/semiconductor via links and fabrication methods thereof
Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second...
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