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Patent # Description
US-1,005,6330 Electrical antifuse having airgap or solid core
An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The...
US-1,005,6329 Programmable buried antifuse
An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the...
US-1,005,6328 Ruthenium metal feature fill for interconnects
A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a...
US-1,005,6327 SOC with integrated voltage regulator using preformed MIM capacitor wafer
In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit...
US-1,005,6325 Semiconductor package having a trench penetrating a main body
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element...
US-1,005,6324 Trace/via hybrid structure with thermally and electrically conductive support material for increased thermal...
A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method and forming a continuous seed metal...
US-1,005,6323 Semiconductor device and method for manufacturing the same
A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate,...
US-1,005,6322 Interposers, semiconductor devices, method for manufacturing interposers, and method for manufacturing...
An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a...
US-1,005,6321 Semiconductor package and method for routing the package
A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a...
US-1,005,6320 Ceramic capacitors with improved lead designs
An electronic component is provided with improved thermal stability. The electronic component comprises at least one capacitive element wherein the capacitive...
US-1,005,6319 Power module package having patterned insulation metal substrate
A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a...
US-1,005,6318 Support terminal integral with die pad in semiconductor package
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first...
US-1,005,6317 Semiconductor package with grounding device and related methods
Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the...
US-1,005,6316 Manufacuting method of semiconductor structure
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in...
US-1,005,6315 Semiconductor device
A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second...
US-1,005,6314 Polymer thermal interface material having enhanced thermal conductivity
A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a...
US-1,005,6313 Power module of square flat pin-free packaging structure
A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module...
US-1,005,6312 Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector...
US-1,005,6311 Electronic circuit module
An electronic circuit module includes a circuit board, electronic components, an embedding layer, and a conductive film. The circuit board has a first principal...
US-1,005,6310 Electrolytic seal
A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first...
US-1,005,6309 Electronic device
Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a...
US-1,005,6307 Semiconductor device
A semiconductor device includes: a semiconductor element; a first bonding pad formed on a surface of the semiconductor element; a test pad formed on the surface...
US-1,005,6306 Test structure for monitoring interface delamination
Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a...
US-1,005,6305 Wafer arrangement, a method for testing a wafer, and a method for processing a wafer
According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component...
US-1,005,6304 Automated optical inspection of unit specific patterning
An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference...
US-1,005,6303 Integration scheme for gate height control and void free RMG fill
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include...
US-1,005,6302 Semiconductor device and related manufacturing method
A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first...
US-1,005,6301 Transistor and fabrication method thereof
A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor...
US-1,005,6300 Methods of forming NMOS and PMOS finFET devices and the resulting product
A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel...
US-1,005,6299 Metal gate structure and manufacturing method thereof
A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation...
US-1,005,6298 Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that...
US-1,005,6297 Modified plasma dicing process to improve back metal cleaving
A method for improving the cleaving of the back metal along the edges of the die of a semiconductor wafer mounted on a deformable plastic film including the...
US-1,005,6296 Workpiece processing method
A processing method of processing a workpiece on which a plurality of intersecting planned dividing lines are set is provided. The processing method includes a...
US-1,005,6295 Method for handling a product substrate, a bonded substrate system and a temporary adhesive
A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the...
US-1,005,6294 Techniques for adhesive control between a substrate and a die
Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a...
US-1,005,6293 Techniques for creating a local interconnect using a SOI wafer
In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a...
US-1,005,6292 Self-aligned lithographic patterning
Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal...
US-1,005,6291 Post spacer self-aligned cuts
The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The...
US-1,005,6290 Self-aligned pattern formation for a semiconductor device
A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of...
US-1,005,6289 Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation...
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on...
US-1,005,6288 Semiconductor device and fabrication method thereof
A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the...
US-1,005,6287 Apparatus for treating surfaces of wafer-shaped articles
A device for processing wafer-shaped articles comprises a closed process chamber. The closed process chamber comprises a housing providing a gas-tight...
US-1,005,6286 Support ring with masked edge
A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge...
US-1,005,6285 Semiconductor wafer device and manufacturing method thereof
A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines...
US-1,005,6284 Electrostatic chuck optimized for refurbishment
A method of manufacturing an electrostatic chuck includes bonding an electrostatic puck to a metal base plate, wherein the electrostatic puck has an electrode...
US-1,005,6283 Apparatus of aligning substrate and method of aligning substrate
An apparatus and a method for aligning a substrate are disclosed. In one aspect, the substrate aligning apparatus includes a stage configured to support a...
US-1,005,6282 Method and system of robot fork calibration and wafer pick-and-place
A robot fork calibration method and system is provided. At least three non-linear arranged lower sensors are provided on a bottom surface of the fork to detect...
US-1,005,6281 Container transport facility
A transport apparatus transports a container that includes a flow hole forming portion in which a flow hole through which gas can flow between the outside and...
US-1,005,6280 Transporting system and transporting unit included therein
A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly...
US-1,005,6279 Semiconductor process equipment
A system for processing a substrate is provided including a first planar motor, a substrate carrier, a first processing chamber, and a first lift. The first...
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