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Patent # Description
US-1,005,6348 Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip...
US-1,005,6347 Bump structure for yield improvement
A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and...
US-1,005,6346 Chip attach frame
A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges...
US-1,005,6345 Conical-shaped or tier-shaped pillar connections
A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical...
US-1,005,6344 Semiconductor device
A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed and...
US-1,005,6343 Packaged semiconductor device with interior polygonal pads
Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure...
US-1,005,6342 Electronic component and electronic device
A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer...
US-1,005,6341 Electronic device with microfilm antenna and related methods
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
US-1,005,6340 Flexible electronic circuit and method for manufacturing same
An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered...
US-1,005,6339 Semiconductor devices
A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer...
US-1,005,6338 Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor...
US-1,005,6337 Thin 3D die with electromagnetic radiation blocking encapsulation
After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the...
US-1,005,6336 Semiconductor device and a method of manufacturing the same
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark....
US-1,005,6335 Prototyping of electronic circuits with edge interconnects
In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities...
US-1,005,6334 Dual metal-insulator-semiconductor contact structure and formulation method
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain...
US-1,005,6333 Stacked multilayer structure and manufacturing method thereof
A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers...
US-1,005,6332 Electronic device with delamination resistant wiring board
This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at...
US-1,005,6331 Programmable via devices with metal/semiconductor via links and fabrication methods thereof
Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second...
US-1,005,6330 Electrical antifuse having airgap or solid core
An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The...
US-1,005,6329 Programmable buried antifuse
An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the...
US-1,005,6328 Ruthenium metal feature fill for interconnects
A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a...
US-1,005,6327 SOC with integrated voltage regulator using preformed MIM capacitor wafer
In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit...
US-1,005,6325 Semiconductor package having a trench penetrating a main body
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element...
US-1,005,6324 Trace/via hybrid structure with thermally and electrically conductive support material for increased thermal...
A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method and forming a continuous seed metal...
US-1,005,6323 Semiconductor device and method for manufacturing the same
A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate,...
US-1,005,6322 Interposers, semiconductor devices, method for manufacturing interposers, and method for manufacturing...
An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a...
US-1,005,6321 Semiconductor package and method for routing the package
A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a...
US-1,005,6320 Ceramic capacitors with improved lead designs
An electronic component is provided with improved thermal stability. The electronic component comprises at least one capacitive element wherein the capacitive...
US-1,005,6319 Power module package having patterned insulation metal substrate
A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a...
US-1,005,6318 Support terminal integral with die pad in semiconductor package
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first...
US-1,005,6317 Semiconductor package with grounding device and related methods
Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the...
US-1,005,6316 Manufacuting method of semiconductor structure
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in...
US-1,005,6315 Semiconductor device
A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second...
US-1,005,6314 Polymer thermal interface material having enhanced thermal conductivity
A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a...
US-1,005,6313 Power module of square flat pin-free packaging structure
A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module...
US-1,005,6312 Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector...
US-1,005,6311 Electronic circuit module
An electronic circuit module includes a circuit board, electronic components, an embedding layer, and a conductive film. The circuit board has a first principal...
US-1,005,6310 Electrolytic seal
A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first...
US-1,005,6309 Electronic device
Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a...
US-1,005,6308 Molded composite enclosure for integrated circuit assembly
Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure...
US-1,005,6307 Semiconductor device
A semiconductor device includes: a semiconductor element; a first bonding pad formed on a surface of the semiconductor element; a test pad formed on the surface...
US-1,005,6306 Test structure for monitoring interface delamination
Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a...
US-1,005,6305 Wafer arrangement, a method for testing a wafer, and a method for processing a wafer
According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component...
US-1,005,6304 Automated optical inspection of unit specific patterning
An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference...
US-1,005,6303 Integration scheme for gate height control and void free RMG fill
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include...
US-1,005,6302 Semiconductor device and related manufacturing method
A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first...
US-1,005,6301 Transistor and fabrication method thereof
A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor...
US-1,005,6300 Methods of forming NMOS and PMOS finFET devices and the resulting product
A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel...
US-1,005,6299 Metal gate structure and manufacturing method thereof
A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation...
US-1,005,6298 Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that...
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