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Patent # Description
US-1,005,6297 Modified plasma dicing process to improve back metal cleaving
A method for improving the cleaving of the back metal along the edges of the die of a semiconductor wafer mounted on a deformable plastic film including the...
US-1,005,6296 Workpiece processing method
A processing method of processing a workpiece on which a plurality of intersecting planned dividing lines are set is provided. The processing method includes a...
US-1,005,6295 Method for handling a product substrate, a bonded substrate system and a temporary adhesive
A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the...
US-1,005,6294 Techniques for adhesive control between a substrate and a die
Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a...
US-1,005,6293 Techniques for creating a local interconnect using a SOI wafer
In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a...
US-1,005,6292 Self-aligned lithographic patterning
Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal...
US-1,005,6291 Post spacer self-aligned cuts
The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The...
US-1,005,6290 Self-aligned pattern formation for a semiconductor device
A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of...
US-1,005,6289 Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation...
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on...
US-1,005,6288 Semiconductor device and fabrication method thereof
A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the...
US-1,005,6287 Apparatus for treating surfaces of wafer-shaped articles
A device for processing wafer-shaped articles comprises a closed process chamber. The closed process chamber comprises a housing providing a gas-tight...
US-1,005,6286 Support ring with masked edge
A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge...
US-1,005,6285 Semiconductor wafer device and manufacturing method thereof
A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines...
US-1,005,6284 Electrostatic chuck optimized for refurbishment
A method of manufacturing an electrostatic chuck includes bonding an electrostatic puck to a metal base plate, wherein the electrostatic puck has an electrode...
US-1,005,6283 Apparatus of aligning substrate and method of aligning substrate
An apparatus and a method for aligning a substrate are disclosed. In one aspect, the substrate aligning apparatus includes a stage configured to support a...
US-1,005,6282 Method and system of robot fork calibration and wafer pick-and-place
A robot fork calibration method and system is provided. At least three non-linear arranged lower sensors are provided on a bottom surface of the fork to detect...
US-1,005,6281 Container transport facility
A transport apparatus transports a container that includes a flow hole forming portion in which a flow hole through which gas can flow between the outside and...
US-1,005,6280 Transporting system and transporting unit included therein
A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly...
US-1,005,6279 Semiconductor process equipment
A system for processing a substrate is provided including a first planar motor, a substrate carrier, a first processing chamber, and a first lift. The first...
US-1,005,6278 Apparatus and method for transferring electronic devices
The present invention relates to an apparatus for transferring electronic devices from a holding unit to a processing station. The apparatus comprises first and...
US-1,005,6277 Polishing method
A polishing method capable of obtaining a stable film thickness without being affected by a difference in measurement position is disclosed. The polishing...
US-1,005,6276 Fluid monitoring system and method for semiconductor fabrication tools
A system and method provide for monitoring and controlling fluid flow in semiconductor manufacturing apparatuses. The method and system include a vortex flow...
US-1,005,6275 Immersion de-taping
Embodiments using immersion de-taping are described. A substrate having a substrate tape attached thereto is provided. The substrate includes electrically...
US-1,005,6274 System and method for forming a sealed chamber
According to an embodiment of the invention, there is provided a system, comprising: a first chamber; a second chamber; a chuck; a movement system; wherein the...
US-1,005,6273 Heating apparatus, substrate heating apparatus, and method of manufacturing semiconductor device
A heating apparatus includes a heater, an electron reflection plate, a filament arranged between the heater and the electron reflection plate, a heating power...
US-1,005,6272 Gas-controlled bonding platform for edge defect reduction during wafer bonding
A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding...
US-1,005,6271 Metal etch system
Embodiments of systems and methods of etching material from the surface of a wafer are provided. In one representative embodiment, an apparatus comprises a...
US-1,005,6270 Substrate treating apparatus and substrate treating method
Disclosed is a substrate treating apparatus including a substrate holder, a rotating drive unit, a treatment liquid supplying unit, an exterior cup, and an...
US-1,005,6269 Substrate liquid processing apparatus
Gas-liquid separation of an exhaust gas from a liquid processing unit can be improved. A substrate liquid processing apparatus includes a liquid processing...
US-1,005,6268 Limiting electronic package warpage
An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be...
US-1,005,6267 Substrate design for semiconductor packages and method of forming same
An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of...
US-1,005,6266 Method for manufacturing a resistive device for a memory or logic circuit
A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first...
US-1,005,6265 Directed self-assembly process with size-restricted guiding patterns
A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method...
US-1,005,6264 Atomic layer etching of GaN and other III-V materials
Provided herein are ALE methods of removing III-V materials such as gallium nitride (GaN) and related apparatus. In some embodiments, the methods involve...
US-1,005,6263 Method of processing SiC wafer
A SiC wafer is processed by a laser beam having a wavelength that transmits SiC to form a peeling plane in a region of the wafer which corresponds to a device...
US-1,005,6262 Non-volatile memory having individually optimized silicide contacts and process therefor
In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control...
US-1,005,6261 P type MOSFET
Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an...
US-1,005,6260 Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same
A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the...
US-1,005,6259 Single conductor alloy as diffusion barrier system and simulataneous OHMIC contact to N- and P-type silicon carbide
Use of a single alloy conductor to form simultaneous ohmic contacts (SOC) to n- and p-type 4H-SiC. The single alloy conductor also is an effective diffusion...
US-1,005,6258 Self-aligned double spacer patterning process
A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer...
US-1,005,6257 Methods for forming fine patterns using spacers
There is provided a method for forming fine patterns. The method includes forming a pattern divider on an underlying layer, forming a mask layer on the...
US-1,005,6256 Method of priming photoresist before application of a shrink material in a lithography process
A photoresist layer is formed over a patternable layer. The photoresist layer containing a negative tone photoresist material. An exposure process is performed...
US-1,005,6255 Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin...
US-1,005,6254 Methods for removal of selected nanowires in stacked gate all around architecture
A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first...
US-1,005,6253 Method for forming a vertical hetero-stack and a device including a vertical hetero-stack
Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to...
US-1,005,6252 Process of forming nitride semiconductor layers
A process of forming a semiconductor device by use of a MOCVD technique is disclosed. The semiconductor device, which is made of primarily nitride semiconductor...
US-1,005,6251 Hetero-integration of III-N material on silicon
A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench....
US-1,005,6249 Atomic layer deposition of antimony oxide films
Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony...
US-1,005,6248 Method for measuring overall concentration of oxidizing substances, substrate cleaning method, and substrate...
To allow online monitoring of the overall concentration of oxidizing substances in electrolyzed sulfuric acid, for example, in a cleaning system, absorbance...
US-1,005,6247 Method of manufacturing silicon carbide semiconductor device
In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially...
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