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Patent # Description
US-1,006,2798 Multiband double junction photodiode and related manufacturing process
A photodiode structure is based on the use of a double junction sensitive to different wavelength bands based on a magnitude of a reverse bias applied to the...
US-1,006,2797 Method of making a IV-VI/Silicon thin-film tandem solar cell
A simple manufacturing method is provided for the fabrication of the IV-VI group of semiconductor films on inexpensive substrates for highly efficient tandem or...
US-1,006,2796 Photovoltaic system, module holder system and reflector
A photovoltaic system has at least two bifacial solar modules, which are respectively held in a module holder, and a reflector. The module holders are...
US-1,006,2795 Sealing sheet for solar cell
A solar cell encapsulant sheet including a resin layer (S) formed of a resin composition containing an olefine-based resin, wherein the storage elastic modulus...
US-1,006,2794 Resonant-cavity infrared photodetectors with fully-depleted absorbers
Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the...
US-1,006,2793 High efficiency quantum well waveguide solar cells and methods for constructing the same
Photon absorption, and thus current generation, is hindered in conventional thin-film solar cell designs, including quantum well structures, by the limited path...
US-1,006,2792 Method of making a CZTS/silicon thin-film tandem solar cell
A method of making a CZTS/inorganic thin-film tandem solar cell including depositing a textured buffer layer on a substrate, depositing a metal-inorganic film...
US-1,006,2791 Self-aligned metal oxide thin film transistor and method of making same
A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel...
US-1,006,2790 Semiconductor device and electronic device
To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high...
US-1,006,2789 Thin film transistor and operating method thereof
A thin film includes a substrate, a bottom gate, a channel layer, a source and a drain, and a top gate. The bottom gate is disposed on the substrate. The...
US-1,006,2788 Semiconductor on insulator devices containing permanent charge
A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is...
US-1,006,2787 FinFET
A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain...
US-1,006,2786 Semiconductor device and method for fabricating the same
A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench...
US-1,006,2785 Fin field-effect transistor (FinFET) with reduced parasitic capacitance
A semiconductor device includes a substrate, a plurality of fins on the substrate, wherein the plurality of fins each include a fin channel region, first...
US-1,006,2784 Self-aligned gate hard mask and method forming same
A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric,...
US-1,006,2783 Silicon germanium fin channel formation
A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying...
US-1,006,2782 Method of manufacturing a semiconductor device with multilayered channel structure
A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a...
US-1,006,2781 MOS devices having epitaxy regions with reduced facets
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the...
US-1,006,2780 FinFET device
A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one...
US-1,006,2779 Semiconductor device and manufacturing method thereof
A method of manufacturing a Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, and part of the upper layer is...
US-1,006,2778 Semiconductor device
A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the...
US-1,006,2777 Trench gate trench field plate vertical MOSFET
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the...
US-1,006,2776 Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V...
US-1,006,2775 GaN-based power electronic device and method for manufacturing the same
A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an...
US-1,006,2774 Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
A semiconductor device includes a plurality of gate trenches formed in a semiconductor layer; a gate electrode filled via a gate insulating film in the...
US-1,006,2773 Semiconductor device having a transistor and first and second embedded layers
The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a...
US-1,006,2772 Preventing bridge formation between replacement gate and source/drain region through STI structure
A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the...
US-1,006,2771 Low temperature poly-silicon thin film transistor and method of manufacturing the same
The present disclosure relates to a low temperature poly-silicon thin film transistor and a method of preparing the same. The low temperature poly-silicon thin...
US-1,006,2770 Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect...
A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is...
US-1,006,2769 Methods of fabricating semiconductor devices
A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device comprises: a semiconductor substrate with an active area...
US-1,006,2768 Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is...
US-1,006,2767 Memory cell and fabrication method thereof
Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate...
US-1,006,2766 Hetero-junction schottky diode device
A hetero-junction Schottky diode device includes a buffer layer, at least one channel layer, at least one barrier layer and a Schottky metal layer. The buffer...
US-1,006,2765 Nonvolatile memory device including multiple planes
A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit...
US-1,006,2764 Semiconductor device having void between gate electrode and sidewall spacer and manufacturing method thereof
A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate,...
US-1,006,2763 Method and apparatus for selectively forming nitride caps on metal gate
A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed...
US-1,006,2762 Semiconductor devices having low contact resistance and low current leakage
The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical...
US-1,006,2761 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes steps of forming a trench in a surface of a semiconductor substrate of a first conductivity type in a...
US-1,006,2760 Semiconductor device
A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a...
US-1,006,2759 Silicon carbide semiconductor device and method for manufacturing same
A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation...
US-1,006,2758 Semiconductor device
A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a...
US-1,006,2757 Semiconductor device with buried metallic region, and method for manufacturing the semiconductor device
A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding...
US-1,006,2756 Semiconductor structure including a doped buffer layer and a channel layer and a process of forming the same
A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer,...
US-1,006,2755 Nanotube termination structure for power semiconductor devices
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination...
US-1,006,2754 Semiconductor devices and methods of fabricating the same
A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and...
US-1,006,2753 Semiconductor device
A semiconductor device includes a semiconductor substrate having a drift layer, a base layer, a collector layer and a cathode layer. The semiconductor substrate...
US-1,006,2752 Fabrication of nanowire vertical gate devices
A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire,...
US-1,006,2751 Semiconductor device
A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure...
US-1,006,2750 Semiconductor device and method of manufacturing semiconductor device
An active region through which current flows in a semiconductor device includes an n.sup.--type silicon carbide epitaxial layer formed on a front surface of an...
US-1,006,2749 High voltage semiconductor devices and methods of making the devices
Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The...
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