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Patent # Description
US-1,006,2698 P-channel multi-time programmable (MTP) memory cells
Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an...
US-1,006,2697 Semiconductor device without a break region
A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a...
US-1,006,2695 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS)...
US-1,006,2694 Patterned gate dielectrics for III-V-based CMOS circuits
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed...
US-1,006,2693 Patterned gate dielectrics for III-V-based CMOS circuits
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed...
US-1,006,2692 Field effect transistors with reduced parasitic resistances and method
Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during...
US-1,006,2691 Semiconductor device having contact plug and method of forming the same
A semiconductor device includes merged contact plugs. A multi-fin active having N sub-fins is formed in a substrate. A contact plug is formed on the impurity...
US-1,006,2690 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related...
A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the...
US-1,006,2689 Method to fabricate vertical fin field-effect-transistors
A FinFET-type device is formed having a fin structure with vertically-oriented source/drain regions (with lightly doped extensions) and a channel region...
US-1,006,2688 Semiconductor device with epitaxial source/drain
A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first...
US-1,006,2687 Stack MOM capacitor structure for CIS
A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a capacitor on the interlayer...
US-1,006,2686 Reverse bipolar junction transistor integrated circuit
A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region...
US-1,006,2684 Transition frequency multiplier semiconductor device
A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first...
US-1,006,2683 Compound semiconductor transistor and high-Q passive device single chip integration
An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound...
US-1,006,2682 Low capacitance bidirectional transient voltage suppressor
A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp...
US-1,006,2681 SOI integrated circuit equipped with a device for protecting against electrostatic discharges
A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty...
US-1,006,2680 Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having...
Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related...
US-1,006,2679 Apparatuses and methods for forming die stacks
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base...
US-1,006,2678 Proximity coupling of interconnect packaging systems and methods
Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed...
US-1,006,2677 Back-to-back solid state lighting devices and associated methods
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can...
US-1,006,2676 Multilayer chipset structure
A multilayer chipset structure is provided. The chips can be arranged in a stacking structure with multilayer circuit board. Each circuit board is formed with...
US-1,006,2675 Micro-LED array display devices
Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a...
US-1,006,2674 Systems and methods for display formation using photo-machinable material substrate layers
Embodiments are related to scalable surface structure (e.g., a well or other structure) formation in a substrate and, more particularly, to systems and methods...
US-1,006,2673 PC-LED module with enhanced white rendering and conversion efficiency
The invention provides a lighting device (100) comprising: --a first solid state light source (10), configured to provide UV radiation (11) having a wavelength...
US-1,006,2672 Light source module
A light source module according to an embodiment includes: a flexible printed circuit board that has first and second pads; and a plurality of light emitting...
US-1,006,2671 Circuit board embedding a power semiconductor chip
A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load...
US-1,006,2670 Radio frequency system-in-package with stacked clocking crystal
A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and...
US-1,006,2669 Semiconductor device
A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer...
US-1,006,2668 Semiconductor electronic device with improved testing features and corresponding packaging method
An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit...
US-1,006,2667 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-1,006,2666 Catch flexure systems, devices and methods
Various systems, devices and methods are provided for interconnection between wafers and/or chips using catch flexures. In one example, among others, a catch...
US-1,006,2665 Semiconductor packages with thermal management features for reduced thermal crosstalk
An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour...
US-1,006,2664 Semiconductor packaging device with heat sink
A semiconductor packaging device includes: a first chip disposed separately from the first chip on a substrate; a second chip disposed on the substrate, wherein...
US-1,006,2663 Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the...
A semiconductor assembly with built-in stiffener and integrated dual routing circuitries is characterized in that a semiconductor device and a first routing...
US-1,006,2662 Integrated fan-out package structures with recesses in molding compound
A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die...
US-1,006,2661 Package-on-package assembly with wire bonds to encapsulation surface
Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A...
US-1,006,2660 Anisotropic conductive film including a reflective layer
An anisotropic conductive film (ACF) is disclosed. In one approach, the ACF includes a non-reflective adhesive layer including a top surface, a plurality of...
US-1,006,2659 System and method for an improved fine pitch joint
Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad...
US-1,006,2658 Electronic component and electronic device
A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer...
US-1,006,2657 Method for manufacturing alloy bump
In order to manufacture an alloy bump, a resist pattern having openings which expose a substrate is formed on the substrate, an under-bump metal is formed on...
US-1,006,2656 Composite bond structure in stacked semiconductor structure
A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the...
US-1,006,2655 Semiconductor device
A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest...
US-1,006,2654 Semicondcutor structure and semiconductor manufacturing process thereof
A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold...
US-1,006,2653 Semiconductor device and method for manufacturing same
According to one embodiment, the recess has a side surface and a bottom surface. The side surface is continuous with the major surface. The bottom surface is...
US-1,006,2652 Fan-out semiconductor package and method of manufacturing same
The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a...
US-1,006,2651 Packaging substrate and electronic package having the same
A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to...
US-1,006,2650 Semiconductor device, and semiconductor chip having chip identification information
A semiconductor device employs at least one of semiconductor chip groups. The semiconductor device includes a semiconductor chip included in the semiconductor...
US-1,006,2649 Package substrate
This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package...
US-1,006,2648 Semiconductor package and method of forming the same
An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the...
US-1,006,2647 Interconnect structure having tungsten contact copper wiring
Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect...
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