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Patent # Description
US-1,006,2646 Semiconductor integrated circuit and electronic system including the same
A semiconductor integrated circuit comprising: a first macro cell including a first power line in a first wiring layer; a second macro cell adjacent to the...
US-1,006,2645 Interconnect structure for semiconductor devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a...
US-1,006,2644 Copper interconnect for improving radio frequency (RF) silicon-on-insulator (SOI) switch field effect...
A radio frequency (RF) switch includes a plurality of silicon-on-insulator (SOI) CMOS transistors. A first metal layer (M1) includes traces that connect the SOI...
US-1,006,2643 Nickel-silicon fuse for FinFET structures
Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate. The...
US-1,006,2642 Semiconductor device with inductively coupled coils
Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a...
US-1,006,2641 Integrated circuits including a dummy metal feature and methods of forming the same
Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an...
US-1,006,2640 Semiconductor devices including sealing regions and decoupling capacitor regions
Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing...
US-1,006,2639 Integrated circuit device with plating on lead interconnection point and method of forming the device
An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an...
US-1,006,2638 Semiconductor package and a method for manufacturing a semiconductor device
A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top...
US-1,006,2637 Method of manufacture for a semiconductor device
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal...
US-1,006,2636 Integration of thermally conductive but electrically isolating layers with semiconductor devices
A semiconductor structure includes a semiconductor wafer having at least one semiconductor device integrated in a first device layer, a thermally conductive but...
US-1,006,2635 Double-faced cooling-type power module
A double-facing cooling-type power module has coolers on both sides. The power module includes: a first switch having the coolers on both sides; a second switch...
US-1,006,2634 Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the...
US-1,006,2633 Substrate unit
Provided is a substrate unit configured to improve heat dissipation efficiency while preventing workability from degrading at the time of assembly. A substrate...
US-1,006,2632 Semiconductor device having improved heat dissipation efficiency
A semiconductor device includes a base plate, a case, a power semiconductor element, and a control semiconductor element. Case is provided on base plate. Power...
US-1,006,2631 Power module
A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower...
US-1,006,2630 Water and ion barrier for the periphery of III-V semiconductor dies
A semiconductor die includes an III-V semiconductor body having a periphery devoid of active devices, the periphery terminating at an edge face of the...
US-1,006,2629 Antenna impedance matching and aperture tuning circuitry
Antenna aperture tuning circuitry includes a first signal path and a second signal path coupled in parallel between an antenna radiating element and ground. A...
US-1,006,2628 Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
US-1,006,2627 Semiconductor device
According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the...
US-1,006,2626 Semiconductor device and manufacturing method thereof
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable...
US-1,006,2625 Underfill material and method for manufacturing semiconductor device using the same
An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same...
US-1,006,2624 Silicon package for embedded semiconductor chip and power converter
A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second...
US-1,006,2623 Semiconductor package substrate, package system using the same and method for manufacturing thereof
A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating...
US-1,006,2622 Electrolytic seal
A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first...
US-1,006,2621 Power semiconductor device module having mechanical corner press-fit anchors
A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A...
US-1,006,2620 Housing assembly and memory device
A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the...
US-1,006,2619 Air gap spacer implant for NZG reliability fix
A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation...
US-1,006,2618 Method and structure for formation of replacement metal gate field effect transistors
Embodiments of the present invention provide a process that maintains a "keep cap" metal nitride layer on PFET devices within a CMOS structure. The keep cap...
US-1,006,2617 Method and structure for SRB elastic relaxation
A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the...
US-1,006,2616 Method of manufacturing a CMOS transistor
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate...
US-1,006,2615 Stacked nanowire devices
A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is...
US-1,006,2614 FinFET device
The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a...
US-1,006,2613 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function...
US-1,006,2612 Method and system for constructing FINFET devices having a super steep retrograde well
Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin...
US-1,006,2611 Encapsulated semiconductor package and method of manufacturing thereof
Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a...
US-1,006,2610 Method of producing an opening with smooth vertical sidewall in a semiconductor substrate
An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles,...
US-1,006,2609 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal...
US-1,006,2608 Semiconductor devices comprising nickel- and copper-containing interconnects
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate...
US-1,006,2607 Methods for producing interconnects in semiconductor devices
A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic...
US-1,006,2605 Via and chamfer control for advanced interconnects
Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is...
US-1,006,2604 Semiconductor device and method for fabricating the same
A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a...
US-1,006,2603 Air-gap scheme for BEOL process
The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which...
US-1,006,2602 Method of etching a porous dielectric material
The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at...
US-1,006,2601 Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure...
US-1,006,2600 System and method for bi-facial processing of substrates
A system for processing substrates in plasma chambers, such that all substrates transport and loading/unloading operations are performed in atmospheric...
US-1,006,2599 Automated replacement of consumable parts using interfacing chambers
A cluster tool assembly includes a vacuum transfer module, a process module having a first side connected to the vacuum transfer module. An isolation valve...
US-1,006,2598 Thermal processing susceptor
In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim...
US-1,006,2597 High voltage chuck for a probe station
A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under...
US-1,006,2596 Systems and methods for treating substrates with cryogenic fluid mixtures
Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for...
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