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Patent # Description
US-1,006,2610 Method of producing an opening with smooth vertical sidewall in a semiconductor substrate
An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles,...
US-1,006,2609 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal...
US-1,006,2608 Semiconductor devices comprising nickel- and copper-containing interconnects
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate...
US-1,006,2607 Methods for producing interconnects in semiconductor devices
A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic...
US-1,006,2606 Methods of fabricating a semiconductor device having a via structure and an interconnection structure
Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, and forming a middle...
US-1,006,2605 Via and chamfer control for advanced interconnects
Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is...
US-1,006,2604 Semiconductor device and method for fabricating the same
A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a...
US-1,006,2603 Air-gap scheme for BEOL process
The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which...
US-1,006,2602 Method of etching a porous dielectric material
The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at...
US-1,006,2601 Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure...
US-1,006,2600 System and method for bi-facial processing of substrates
A system for processing substrates in plasma chambers, such that all substrates transport and loading/unloading operations are performed in atmospheric...
US-1,006,2599 Automated replacement of consumable parts using interfacing chambers
A cluster tool assembly includes a vacuum transfer module, a process module having a first side connected to the vacuum transfer module. An isolation valve...
US-1,006,2598 Thermal processing susceptor
In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim...
US-1,006,2597 High voltage chuck for a probe station
A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under...
US-1,006,2596 Systems and methods for treating substrates with cryogenic fluid mixtures
Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for...
US-1,006,2595 Systems and methods for wafer alignment
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
US-1,006,2594 End effector device
An end effector device is provided with a hand; a plurality of holding portions that are provided to the hand, and that hold a plurality of semiconductor wafers...
US-1,006,2593 Substrate processing apparatus and substrate processing method
During a teaching operation regarding a transport mechanism, a hand of the transport mechanism is moved to a tentative target position in a substrate supporter,...
US-1,006,2592 Substrate processing apparatus
A substrate processing apparatus includes a substrate retaining mechanism; a detecting unit detecting a placed state of the substrate retained by the substrate...
US-1,006,2591 Equipment platform system and wafer transfer method thereof
An equipment platform system and a wafer transfer method used to a wafer processing is provided. The equipment platform system comprises: a working platform,...
US-1,006,2590 Front opening ring pod
A pod for exchanging consumable parts with a process module includes a base plate having a front side, a back side, and first and second lateral sides. A first...
US-1,006,2589 Front opening ring pod
A pod for exchanging consumable parts with a process module includes a base plate having a front side, a back side, and first and second lateral sides. A first...
US-1,006,2588 Flexible support substrate for transfer of semiconductor devices
An apparatus for transferring a semiconductor die from a wafer tape to a product substrate. The apparatus includes a wafer frame configured to hold the wafer...
US-1,006,2587 Pedestal with multi-zone temperature control and multiple purge capabilities
Substrate support assemblies for a semiconductor processing apparatus are described. The assemblies may include a pedestal and a stem coupled with the pedestal....
US-1,006,2586 Chemical fluid processing apparatus and chemical fluid processing method
A chemical fluid processing apparatus and a chemical fluid processing method are described, to treat a substrate with a plurality of chemical fluids such that...
US-1,006,2585 Oxygen compatible plasma source
Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber...
US-1,006,2584 Method for forming semiconductor structure
A method for forming a semiconductor structure is disclosed. The method includes the following steps. A first pattern structure and a second pattern structure...
US-1,006,2583 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,006,2582 Fabrication method of package having ESD and EMI preventing functions
A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure...
US-1,006,2581 Methods of forming an isolation structure and methods of manufacturing a semiconductor device including the same
A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using...
US-1,006,2580 Etchant, etching method using same, and method for manufacturing semiconductor substrate product
Provided is an etchant for a semiconductor process, which contains a sulfonic acid compound, a halogen ion, nitric acid or a nitric acid ion, an organic cation,...
US-1,006,2579 Selective SiN lateral recess
Exemplary methods for laterally etching silicon nitride may include flowing a fluorine-containing precursor and an oxygen-containing precursor into a remote...
US-1,006,2578 Methods for etch of metal and metal-oxide films
A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a...
US-1,006,2577 Method of fabricating III-V fin structures and semiconductor device with III-V fin structures
A method of fabricating III-V fin structures includes providing numerous fins. Then, a group III-V material layer is formed to encapsulate an upper portion of...
US-1,006,2576 Method for plasma etching a workpiece
A method of plasma etching one or more features in a silicon substrate includes performing a main etch using a cyclical etch process in which a deposition step...
US-1,006,2575 Poly directional etch by oxidation
Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon surface on a...
US-1,006,2574 Wafer polishing apparatus and method
A wafer polishing apparatus capable of maintaining a drive ring in a flat state and a wafer polishing method are provided. In the wafer polishing apparatus and...
US-1,006,2573 Embedded SONOS with triple gate oxide and manufacturing method of the same
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate...
US-1,006,2572 Semiconductor structure and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate,...
US-1,006,2571 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, forming a plurality of reference patterns, arranged at a first...
US-1,006,2570 Semiconductor device and method for manufacturing the same
An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for...
US-1,006,2569 Epitaxial wafer manufacturing method and epitaxial wafer
Provided is a method of manufacturing an epitaxial wafer having an excellent gettering capability while suppressing formation of epitaxial defects. The method...
US-1,006,2568 Chemical vapor deposition method for fabricating two-dimensional materials
A method of synthesis of two-dimensional metal chalcogenide monolayers, such as WSe.sub.2 and MoSe.sub.2, is based on a chemical vapor deposition approach that...
US-1,006,2567 Reducing autodoping of III-V semiconductors by atomic layer epitaxy (ALE)
In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate,...
US-1,006,2566 Semiconductor device, display substrate, display device, and method for manufacturing polysilicon film
A semiconductor device, comprising a base substrate, a buffer layer and a polysilicon layer film, wherein the base substrate, the buffer layer and the...
US-1,006,2565 Nitride semiconductor element and nitride semiconductor package
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device...
US-1,006,2564 Method of selective gas phase film deposition on a substrate by modifying the surface using hydrogen plasma
According to one embodiment of the invention, a method is provided for selective surface deposition. In one example, the method includes providing a substrate...
US-1,006,2563 Selective atomic layer deposition with post-dose treatment
Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition are...
US-1,006,2562 Method of manufacturing semiconductor device, substrate processing apparatus and recording medium
According to the present invention, when a film is formed on a substrate, a film-forming rate or film quality is stabilized. There is provided a method of...
US-1,006,2561 High-pressure annealing and reducing wet etch rates
Methods are described for reducing the wet etch rate of dielectric films formed on a patterned substrate by flowing the material into gaps during deposition....
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